CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 161

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

20.3.21 CS_SLEW
This register enables and controls a fast slewing mode for the relaxation oscillator.
For additional information, refer to the
Bit
7:1
0
PSoC CY8C20x34 TRM, Version 1.0
Individual Register Names and Addresses:
CS_SLEW : 0,A8h
Access : POR
Bit Name
FastSlew[6:0]
FS_EN
Name
CapSense Slew Control Register
7
6
Description
This 7-bit value sets a counter, clocked at the IMO frequency. While the counter is counting down
from this value, the relaxation oscillator edge slews at the maximum gain setting. During this interval,
the IRANGE bits in the CS_CR2 register are internally set to maximum (11b). At the end of the inter-
val, the user-defined IRANGE level is restored, so that the relaxation oscillator continues slewing with
a slower edge rate to the target voltage threshold. If the FS_EN bit is low, the FastSlew setting has no
effect.
After each edge of the relaxation oscillator, the counter is re-loaded and the fast slewing interval re-
occurs, followed by the slower edge rate at the end of the count down.
Note that the IRANGE bits in the CS_CR2 register will always read the user-defined setting. Because
the IRANGE value is forced to maximum during this interval, the increase in the edge rate can be 1X,
2X, 4X, or 8X, depending on the programmed value of the IRANGE bits.
0000000b
0000001b
…
1111111b
Enable bit for the Fast Slew mode
0
1
Register Definitions on page 76
Fast slew mode disabled.
Fast slew mode enabled. After each relaxation oscillator transition, the relaxation oscillator
runs with a higher current for a time controlled by the FastSlew bits.
No fast edge rate interval
Minimum fast edge rate interval (1 IMO period)
Maximum fast edge rate interval (127 IMO period)
5
FastSlew[6:0]
RW : 0
4
in the CapSense Module chapter .
3
2
1
0,A8h
CS_SLEW
FS_EN
RW : 0
0,A8h
0
161