CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 80

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

CapSense Module
10.2.9
The CapSense Slew Control Register (CS_SLEW) enables
and controls a fast slewing mode for the relaxation oscillator.
Bits 7 to 1: FastSlew[6:0]. This 7-bit count sets the time
interval, in IMO cycles, for a faster slew rate on the relax-
ation oscillator edges. The interval applies to both rising and
10.2.10
The Current DAC Data Register (IDAC_D) specifies the 8-
bit multiplying factor that determines the output DAC cur-
rent.
80
0,A8h
0,FDh
Address
Address
IDAC_D
CS_SLEW
CS_SLEW Register
IDAC_D Register
Name
Name
Bit 7
Bit 7
Bit 6
Bit 6
Bit 5
Bit 5
FastSlew[6:0]
Bit 4
Bit 4
IDACDATA[7:0]
falling edges. This timer value has no effect unless the
FS_EN bit is set high.
Bit 0: FS_EN. This bit enables the fast slewing interval on
each edge of the relaxation oscillator.
For additional information, refer to the
page
Bits 7 to 0: IDACDATA[7:0]. The 8-bit value in this register
sets the current driven onto the analog global mux bus when
the current DAC mode is enabled.
For additional information, refer to the
page
161.
180.
Bit 3
Bit 3
Bit 2
Bit 2
PSoC CY8C20x34 TRM, Version 1.0
Bit 1
Bit 1
CS_SLEW register on
FS_EN
IDAC_D register on
Bit 0
Bit 0
Access
RW : 00
Access
RW : 00