CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 121

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

Control Register
18.2.3
The SPI Control Register (SPI_CR) is the SPI’s control reg-
ister.
Bit 7: LSb First. This bit determines how the serial data is
shifted out, either LSb or MSb first.
Bit 6: Overrun. This status bit indicates whether or not
there was a Receive Buffer overrun. A read from the
Receive buffer, after each received byte, must be performed
before the reception of the next byte to avoid an overrun
condition.
Bit 5: SPI Complete. This status bit indicates the comple-
tion of a transaction. A read from this register clears this bit.
Bit 4: TX Reg Empty. This status bit indicates whether or
not the transmit register is empty.
Table 18-4. SPI Control Register Descriptions
PSoC CY8C20x34 TRM, Version 1.0
0,2Bh
LEGEND
#
Address
Bit #
Access is bit specific. Refer to the register detail for additional information.
7
6
5
4
3
2
1
0
LSb First
Overrun
SPI
Complete
TX Reg
Empty
TX Reg Full
Clock
Phase
Clock
Polarity
Enable
SPI_CR
Name
SPI_CR Register
Name
Read/
Write
Read
Only
Read
Only
Read
Only
Read
Only
Read/
Write
Read/
Write
Read/
Write
Access
LSb First
Bit 7
0 = Data shifted out MSb First.
1 = Data shifted out LSb First.
0 = No overrun.
1 = Indicates new byte received before previous one is read.
0 = Transaction in progress.
1 = Transaction is complete. Reading SPI_CR clears this bit.
0 = TX register is full.
1 = TX register is empty. Writing SPI_TXR register clears this bit.
0 = RX register is not full.
1 = RX register is full. Reading SPI_RXR register clears this bit.
0 = Data changes on trailing edge.
1 = Data changes on leading clock edge.
0 = Non-inverted, clock idles low (modes 0,2)
1 = Inverted, clock idles high (modes 1,3)
0 = Disable SPI function.
1 = Enable SPI function.
Overrun
Bit 6
Complete
Bit 5
SPI
TX Reg
Empty
Bit 4
Bit 3: RX Reg Full. This status bit indicates a receive reg-
ister full condition.
Bit 2: Clock Phase. This bit determines which edge (rising
and falling) that the data changes on.
Bit 1: Clock Polarity. This bit determines the logic level the
clock codes to in its idle state.
Bit 0: Enable. This bit enables the SPI block.
For additional information, refer to the
page
18.2.3.1
RX Reg Full
144.
Bit 3
Description
SPI Control Register Definitions
Phase
Clock
Bit 2
Polarity
Clock
Bit 1
SPI_CR register on
Enable
Bit 0
Access
# : 00
121
SPI