CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 97

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

This chapter explains the I
designed to implement a complete I2C slave. For a complete table of the I2C registers, refer to the
System Resource Registers” on page
Reference chapter on page
14.1
The I2C communications block is a serial to parallel proces-
sor, designed to interface the PSoC device to a two-wire I2C
serial communications bus. To eliminate the need for exces-
sive M8C microcontroller intervention and overhead, the
block provides I2C specific support for status detection and
generation of framing bits.
Figure 14-1. I
The I2C block controls the data (SDA) and the clock (SCL)
to the external I2C interface, through direct connections to
two dedicated GPIO pins. When I2C is enabled, these GPIO
pins are not available for general purpose use. The PSoC
device firmware interacts with the block through IO (input/
output) register reads and writes, and firmware synchroniza-
tion will be implemented through polling and/or interrupts.
PSoC CY8C20x34 TRM, Version 1.0
14.
SDA_IN
SCL_IN
Architectural Description
I
2
2
DATA_IN
CLK_IN
SYSCLK
C Slave Block Diagram
C Slave
I2C Slave Block
CONFIGURATION[7:0]
CONTROL[7:0]
Registers
DATA[7:0]
2
C™ Slave block and its associated registers. The I2C communications block is a serial processor
139.
DATA_OUT
CLK_OUT
INT
90. For a quick reference of all PSoC registers in address order, refer to the
SDA_OUT
SCL_OUT
PSoC I2C features include:
Hardware functionality provides basic I2C control, data, and
status primitives. A combination of hardware support and
firmware command sequencing provides a high degree of
flexibility for implementing the required I2C functionality.
Hardware limitations in regards to I2C are as follows:
1. There is no hardware support for automatic address
2. Since receive and transmitted data are not buffered,
The I2C block is designed to support a set of primitive oper-
ations and detect a set of status conditions specific to the
I2C protocol. These primitive operations and conditions are
manipulated and combined at the firmware level to support
the required data transfer modes. The CPU will set up con-
trol options and issue commands to the unit through IO
writes and obtain status through IO reads and interrupts.
The block operates as a slave. In Slave mode, the unit is
always listening for a Start condition, or sending or receiving
data.
Slave, Transmitter/Receiver operation
Byte processing for low CPU overhead
Interrupt or polling CPU interface
7- or 10-bit addressing (through firmware support)
SMBus operation (through firmware support)
comparison. Every slave address will cause the block to
interrupt the PSoC device and possibly stall the bus.
there is no support for automatic receive acknowledge.
The M8C microcontroller must intervene at the boundary
of each byte and either send a byte or ACK received
bytes.
“Summary Table of the
Register
97