CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 77

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

10.2.2
The CapSense Control Register 1 (CS_CR1) contains addi-
tional CapSense system control options. This register
should never be written to while the block is enabled.
Bit 7: CHAIN. When this bit is a ‘0’, the two 8-bit counters
operate independently. When this bit is a ‘1’, the counters
are chained to operate as a 16-bit counter.
Bits 6 and 5: CLKSEL[1:0]. These
CapSense module frequency of operation according to the
following table.
Bit 4: RLOSEL. When this bit is a ‘0’, the entire CapSense
system runs at the frequency specified in the CLKSEL[1:0]
bits. When this bit is a ‘1’, the High Counter is clocked inde-
pendently by the CapSense RLO clock.
10.2.3
The CapSense Control Register 2 (CS_CR2) contains addi-
tional CapSense system control options.
Bits 7 and 6: IRANGE. These bits scale the IDAC current
output.
Bit 5: IDACDIR. This bit determines whether the IDAC
sinks or sources current to the analog global bus when
enabled.
Bit 4: IDAC_EN. This bit enables manual connection of the
IDAC to the analog global bus.
PSoC CY8C20x34 TRM, Version 1.0
0,A1h
0,A2h
CLKSEL[1:0]
Address
Address
00
01
10
00
01
10
11
11
0
1
CS_CR1
CS_CR2
CS_CR1 Register
IMO
IMO/2
IMO/4
IMO/8
CS_CR2 Register
1X range
2X range
4X range
8X range
IDAC Sources
IDAC Sink
Name
Name
CHAIN
Bit 7
Bit 7
Frequency of Operation
Frequency of Operation
Frequency of Operation
IRANGE
Bit 6
Bit 6
bits
CLKSEL[1:0]
select
IDACDIR
Bit 5
Bit 5
the
IDAC_EN
RLOSEL
Bit 4
Bit 4
Bit 3: INV. Input Invert. When this bit is a ‘1’, the data input
select is inverted. When this bit is a ‘0’, the input polarity is
unchanged.
Bits 2 to 0: INSEL[2:0]. Input Selection. These bits control
the selection of input signals for event control according to
the following table.
For additional information, refer to the
page
Bit 2: PXD_EN. This bit drives a clock to each IO pin that is
enabled for connection to the analog global bus. This clock
alternately connects the pin to the bus, then connects the
pin to ground. The clock rate is selected by the CLKSEL bits
in the CS_CR1 register. In addition, the IDAC sources cur-
rent to the bus. The programmable timer is clocked by this
same clock.
Bit 0: RO_EN. This bit enables the relaxation oscillator.
The internal RO is connected to the analog global bus, and
the capacitance of any connected pins will affect the RO fre-
quency. The oscillator current is set by the value of the
IDAC_D register.
For additional information, refer to the
page
INSEL[1:0]
000
001
010
011
100
101
110
111
154.
155.
Bit 3
Bit 3
INV
Comparator 0
ILO
Comparator 1
RLO Timer Terminal Count
Internal Timer
RLO Timer IRQ
Analog Global Mux Bus
‘0’
PXD_EN
Bit 2
Bit 2
INSEL[2:0]
Bit 1
Bit 1
Selected Input
CS_CR1 register on
CS_CR2 register on
RO_EN
Bit 0
Bit 0
CapSense Module
RW : 00
RW : 00
Access
Access
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