CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 91

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

This chapter discusses the Digital Clocks and their associated registers. It serves as an overview of the clocking options
available in the PSoC devices. For detailed information on specific oscillators, see the individual oscillator chapters in the sec-
tion called
System Resource Registers” on page
Reference chapter on page
13.1
The PSoC M8C core has a large number of clock sources
that increase the flexibility of the PSoC mixed-signal array,
as listed in
Table 13-1. System Clocking Signals and Definitions
PSoC CY8C20x34 TRM, Version 1.0
SYSCLK
CPUCLK
CLK32K
CLK12M
SLEEP
13.
Signal
“PSoC Core” on page
Table 13-1
Architectural Description
Either the direct output of the Internal Main Oscillator or the
direct input of the EXTCLK pin while in external clocking
mode.
SYSCLK is divided down to one of eight possible frequen-
cies, to create CPUCLK which determines the speed of the
M8C. See OSC_CR0 in the Register Definitions section of
this chapter.
The Internal Low Speed Oscillators output. See OSC_CR0 in
the Register Definitions section of this chapter.
The internally generated 12 MHz clock by the IMO. By
default, this clock drives SYSCLK; however, an external clock
may be used by enabling EXTCLK mode. Also, the IMO may
be put into a slow mode using the SLIMO bit which will
change the speed of the IMO and the CLK24M to 6 MHz or
12 MHz.
One of four sleep intervals may be selected from 1.95 ms to 1
second. See OSC_CR0 in the Register Definitions section of
this chapter.
Digital Clocks
and illustrated in
139.
Definition
23. For a complete table of the digital clock registers, refer to the
90. For a quick reference of all PSoC registers in address order, refer to the
Figure
13-1.
13.1.1
The Internal Main Oscillator (IMO) is the foundation upon
which almost all other clock sources in the PSoC mixed-sig-
nal array are based. The default mode of the IMO creates a
12 MHz reference clock that is used by many other circuits
in the PSoC device. The PSoC device has an option to
replace the IMO with an externally supplied clock that will
become the base for all of the clocks the IMO normally
serves. The internal base clock net is called SYSCLK and
may be driven by either the IMO or an external clock (EXT-
CLK).
Whether the external clock or the internal main oscillator is
selected, all PSoC device functions are clocked from a
derivative of SYSCLK or are resynchronized to SYSCLK. All
external asynchronous signals, as well as the internal low
speed oscillator, are resynchronized to SYSCLK for use in
the digital PSoC blocks.
Some PSoC devices contain the option to lower the internal
oscillator’s system clock from 12 MHz to 6 MHz. See the
“Architectural Description” on page
Oscillator chapter, for more information.
The IMO is discussed in detail in the chapter
Oscillator (IMO)” on page
13.1.2
The Internal Low Speed Oscillator (ILO) is always on. The
ILO is available as a general clock, but is also the clock
source for the sleep and watchdog timers.
The ILO is discussed in detail in the chapter
Speed Oscillator (ILO)” on page
Internal Main Oscillator
Internal Low Speed Oscillator
59.
61.
59, in the Internal Main
“Summary Table of the
“Internal Main
“Internal Low
Register
91