CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 64

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

Sleep and Watchdog
9.2
The following are notes regarding sleep as it relates to firm-
ware and application issues.
Note 1 If an interrupt is pending, enabled, and scheduled to
be taken at the instruction boundary after the write to the
sleep bit, the system will not go to sleep. The instruction will
still execute, but it will not be able to set the Sleep bit in the
CPU_SCR0 register. Instead, the interrupt will be taken and
the effect of the sleep instruction is ignored.
Note 2 The Global Interrupt Enable (CPU_F register) does
not need to be enabled to wake the system out of sleep
state. Individual interrupt enables, as set in the interrupt
mask registers, are sufficient. If the Global Interrupt Enable
is not set, the CPU will not service the ISR associated with
that interrupt. However, the system will wake up and con-
tinue executing instructions from the point at which it went to
sleep. In this case, the user must manually clear the pend-
ing interrupt or subsequently enable the Global Interrupt
Enable bit and let the CPU take the ISR. If a pending inter-
rupt is not cleared, it will be continuously asserted. Although
the Sleep bit may be written and the sleep sequence exe-
cuted as soon as the device enters Sleep mode, the Sleep
bit is cleared by the pending interrupt and Sleep mode is
exited immediately.
Note 3 On wake up, the instruction immediately after the
sleep instruction is executed before the interrupt service
routine (if enabled). The instruction after the sleep instruc-
tion is pre-fetched before the system actually goes to sleep.
Therefore, when an interrupt occurs to wake the system up,
the pre-fetched instruction is executed and then the interrupt
service routine is executed. (If the Global Interrupt Enable is
64
Application Overview
not set, instruction execution continues where it left off
before sleep.)
Note 4 Analog power must be turned off by firmware before
going to sleep, to achieve the smallest sleep current. The
system sleep state does not control the analog array. There
are individual power controls for each analog block and glo-
bal power controls in the reference block. These power con-
trols must be manipulated by firmware.
Note 5 If the Global Interrupt Enable bit is disabled, it can be
safely enabled just before the instruction that writes the
sleep bit. It is usually undesirable to get an interrupt on the
instruction boundary, just before writing the sleep bit. This
means that on the return from interrupt, the sleep command
will be executed, possibly bypassing any firmware prepara-
tions that must be made in order to go to sleep. To prevent
this, disable interrupts before preparations are made. After
sleep preparations, enable global interrupts and write the
sleep bit with the two consecutive instructions as follows.
and f,~01h
or f,01h
mov reg[ffh],08h
Due to the timing of the Global Interrupt Enable instruction, it
is not possible for an interrupt to occur immediately after that
instruction. The earliest the interrupt could occur is after the
next instruction (write to the Sleep bit) has been executed.
Therefore, if an interrupt is pending, the sleep instruction is
executed; but as described in Note 1, the sleep instruction
will be ignored. The first instruction executed after the ISR is
the instruction after sleep.
PSoC CY8C20x34 TRM, Version 1.0
// disable global interrupts
// (prepare for sleep, could
// be many instructions)
// enable global interrupts
// Set the sleep bit