CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 109

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

This chapter discusses the System Resets and their associated registers. PSoC devices support several types of resets. The
various resets are designed to provide error-free operation during power up for any voltage ramping profile, to allow for user-
supplied external reset and to provide recovery from errant code operation. For a complete table of the System Reset regis-
ters, refer to the
in address order, refer to the
16.1
When reset is initiated, all registers are restored to their
default states. In the
page
tables and elsewhere it is indicated in the Access column,
values on the right side of the colon, in the register tables.
Minor exceptions are explained below.
The following types of resets can occur in the PSoC device:
n
n
n
n
The occurrence of a reset is recorded in the Status and Con-
trol registers (CPU_SCR0 for POR, XRES, and WDR) or in
the System Status and Control Register 1 (CPU_SCR1 for
IRESS). Firmware can interrogate these registers to deter-
mine the cause of a reset.
PSoC CY8C20x34 TRM, Version 1.0
16.
Power on Reset (POR). This occurs at low supply volt-
age and is comprised of multiple sources.
External Reset (XRES). This active high reset is driven
into the PSoC device on parts that contain an XRES pin.
Watchdog Reset (WDR). This optional reset occurs
when the watchdog timer expires before being cleared
by user firmware. Watchdog reset defaults to off.
Internal Reset (IRES). This occurs during the boot
sequence if the SROM code determines that Flash
reads are not valid.
139, this is indicated by the POR row in the register
Architectural Description
System Resets
“Summary Table of the System Resource Registers” on page
Register Reference chapter on
Register Reference chapter on page
16.2
Power on Reset and External Reset cause toggling on two
GPIO pins, P1[0] and P1[1], as described below and illus-
trated in
mers to synchronize with the PSoC device. All other GPIO
pins are placed in a high impedance state during and imme-
diately following reset.
16.2.1
At power up, the internal POR causes P1[0] to initially drive
a strong high (1) while P1[1] drives a resistive low (0). After
256 sleep oscillator cycles (approximately 8 ms), the P1[0]
signal transitions to a resistive low state. After an additional
256 sleep oscillator clocks, both pins transition to a high
impedance state and normal CPU operation begins. This is
illustrated in
Figure 16-1. P1[1:0] Behavior on Power Up
Internal
139.
Reset
P1[0]
P1[1]
POR Trip
Vdd
Point
Figure 16-1
Pin Behavior During Reset
Figure
GPIO Behavior on Power Up
90. For a quick reference of all PSoC registers
16-1.
R0
S1
T1
and
Figure
T1 = T2 = 256 Sleep Clock Cycles
(approximately 8 ms)
R0
R0
T2
16-2. This allows program-
HiZ
HiZ
109