CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 38

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

RAM Paging
3.2.6
The MVI Write Page Pointer Register (MVW_PP) is used to
set the effective SRAM page for MVI write memory
accesses in a multi-SRAM page PSoC device.
Bit 0: Page Bit. This bit is only used by the MVI [expr], A
instruction, not to be confused with the MVI A, [expr] instruc-
tion covered by the MVR_PP register. This instruction is
considered a write because data is transferred from the
microprocessor's A register (CPU_A) to SRAM.
When an MVI [expr], A instruction is executed in a device
with more than one page of SRAM, the SRAM address that
3.2.7
38
0,D5h
Address
“CPU_F Register” on page
MVW_PP
MVW_PP Register
Related Registers
Name
Bit 7
32.
Bit 6
Bit 5
Bit 4
is written by the instruction is determined by the value of the
least significant bits in this register. However, the pointer for
the MVI [expr], A instruction is always located in the current
SRAM page. See the PSoC Designer Assembly Language
User Guide for more information on the MVI [expr], A
instruction.
The function of this register and the MVI instructions are
independent of the SRAM Paging bits in the CPU_F register.
For additional information, refer to the
page
169.
Bit 3
Bit 2
PSoC CY8C20x34 TRM, Version 1.0
Bit 1
MVW_PP register on
Page Bit
Bit 0
Access
RW : 00