CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 95

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

13.2.2
The Oscillator Control Register 0 (OSC_CR0) is used to
configure various features of internal clock sources and
clock nets.
Bit 6: Disable Buzz. Setting this bit causes the bandgap
and POR/LVD systems to remain powered off continuously
during sleep. In this case, there is no periodic “buzz” (brief
wakeup) of these functions during sleep. This bit has no
effect when the No Buzz bit is set high.
Bit 5: No Buzz. Normally, when the Sleep bit is set in the
CPU_SCR register, all PSoC device systems are powered
down, including the bandgap reference. However, to facili-
tate the detection of POR and LVD events at a rate higher
than the sleep interval, the bandgap circuit is powered up
periodically (for about 60 µ s) at the Sleep System Duty
Cycle, which is independent of the sleep interval and typi-
cally higher. When the No Buzz bit is set, the Sleep System
Duty Cycle value is overridden and the bandgap circuit is
forced to be on during sleep. This results in faster response
to an LVD or POR event (continuous detection as opposed
to periodic), at the expense of slightly higher average sleep
current.
Bits 4 and 3: Sleep[1:0]. The
selections are shown in
approximate based on the accuracy of the internal low
speed oscillator.
Table 13-2. Sleep Interval Selections
PSoC CY8C20x34 TRM, Version 1.0
1,E0h
00b (default)
01b
10b
11b
Sleep Interval
OSC_CR[4:3]
Address
OSC_CR0
OSC_CR0 Register
Name
64
512
4096
32,768
Sleep Timer
Clocks
Bit 7
Table
1.95 ms
15.6 ms
125 ms
1 sec
Sleep Period
(nominal)
available
13-2. Sleep intervals are
Disable Buzz
Bit 6
6 ms
47 ms
375 ms
3 sec
sleep
Watchdog
(nominal)
Period
No Buzz
Bit 5
interval
Bit 4
Sleep[1:0]
Bits 2 to 0: CPU Speed[2:0]. The PSoC M8C may operate
over a range of CPU clock speeds
M8C’s performance and power requirements to be tailored
to the application.
The reset value for the CPU speed bits is 001b. Therefore,
the default CPU speed is one-fourth of the clock source. The
internal main oscillator is the default clock source for the
CPU speed circuit; therefore, the default CPU speed is 3.0
MHz. See
on the supported frequencies for externally supplied clocks.
The CPU frequency is changed with a write to the
OSC_CR0 register. There are eight frequencies generated
from a power-of-two divide circuit which are selected by a 3-
bit code. At any given time, the CPU 8-to-1 clock mux is
selecting one of the available frequencies, which is resyn-
chronized to the 12 MHz master clock at the output.
A slow IMO option is also supported, as discussed in the
IMO chapter in the
This offers an option to lower both system and CPU clock
speed in order to save power.
Table 13-3. OSC_CR0[2:0] Bits: CPU Speed
An automatic protection mechanism is available for systems
that need to run at peak CPU clock speed but cannot guar-
antee a high enough supply voltage for that clock speed.
See the LVDTBEN bit in the
for more information.
For additional information, refer to the
page
000b
001b
010b
011b
100b
101b
110b
111b
Bits
189.
Bit 3
“External Clock” on page 92
750 kHz
1.5 MHz
3 MHz
6 MHz
375 kHz
187.5 kHz
46.8 kHz
23.4 kHz
Main Oscillator
6 MHz Internal
Bit 2
“Architectural Description” on page
CPU Speed[2:0]
1.5 MHz
3.0 MHz
6.0 MHz
12.0 MHz
750 MHz
375 kHz
93.7 kHz
46.8 kHz
12 MHz Internal
Main Oscillator
“VLT_CR Register” on page 115
Bit 1
(Table
OSC_CR0 register on
for more information
Bit 0
13-3), allowing the
EXTCLK/ 8
EXTCLK/ 4
EXTCLK/ 2
EXTCLK/ 1
EXTCLK/ 16
EXTCLK/ 32
EXTCLK/ 128
EXTCLK/ 256
External Clock
Digital Clocks
RW : 01
Access
59.
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