CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 94

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

Digital Clocks
13.2
The following registers are associated with the Digital Clocks and are listed in address order. Each register description has an
associated register table showing the bit structure for that register. The bits in the tables that are grayed out throughout this
manual are reserved bits and are not detailed in the register descriptions that follow. Reserved bits should always be written
with a value of ‘0’. For a complete table of digital clock registers, refer to the
ters” on page
13.2.1
The Output Override to Port 1 Register (OUT_P1) enables
specific internal signals to be output to Port 1 pins. If any
other function, such as I2C, is enabled for output on these
pins, that function has higher priority than the OUT_P1 sig-
nals.
Bit 7: P16D. This bit selects either the TIMEROUT or
CLK32 signals for output on P1[6]. P16EN must be high for
the signal to be output on that pin.
Bit 6: P16EN. This bit enables pin P1[6] for output of the
signal selected by the P16D bit.
Bit 5: P14D. This bit selects either the RO or CMP1 signals
for output on P1[4]. P14EN must be high for the signal to be
output on that pin.
94
1,DDh
Address
Register Definitions
OUT_P1
OUT_P1 Register
90.
Name
P16D
Bit 7
P16EN
Bit 6
P14D
Bit 5
P14EN
Bit 4
Bit 4: P14EN. This bit enables pin P1[4] for output of the
signal selected by the P14D bit.
Bit 3: P12D. This bit selects either the SYSCLK or CS sig-
nals for output on P1[2]. P12EN must be high for the signal
to be output on that pin.
Bit 2: P12EN. This bit enables pin P1[2] for output of the
signal selected by the P12D bit.
Bit 1: P10D. This bit selects either the SLPINT or CMP0
signals for output on P1[0]. P10EN must be high for the sig-
nal to be output on that pin.
Bit 0: P10EN. This bit enables pin P1[0] for output of the
signal selected by the P10D bit.
For additional information, refer to the
page
188.
P12D
Bit 3
“Summary Table of the System Resource Regis-
P12EN
Bit 2
PSoC CY8C20x34 TRM, Version 1.0
P10D
Bit 1
OUT_P1 register on
P10EN
Bit 0
Access
RW : 00