CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 196

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

SLP_CFG
20.4.14 SLP_CFG
This register is used to set the sleep duty cycle.
It is strongly recommended that the user not alter this register’s values. The trim bits are set to factory specifications
and should not be changed.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits should always be written with a value of ‘0’. For additional information, refer to the
65
Bit
7:6
196
Individual Register Names and Addresses:
SLP_CFG: 1,EBh
Access : POR
Bit Name
1,EBh
in the Sleep and Watchdog chapter.
PSSDC[1:0]
Name
Sleep Configuration Register
7
PSSDC[1:0]
RW : 0
6
Description
The value of these bits should not be changed.
00b
01b
10b
11b
Sleep Duty Cycle. Controls the ratios (in numbers of 32.768 kHz clock periods) of “on” time versus
“off” time for PORLVD4, bandgap reference.
1 / 256 (8 ms)
1 / 1024 (31.2 ms)
1 / 64 (2 ms)
1 / 16 (500 ms)
5
4
3
PSoC CY8C20x34 TRM, Version 1.0
2
1,EBh
Register Definitions on page
1
0