CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 175

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

20.3.34 INT_MSK0
This register is used to enable the individual sources’ ability to create pending interrupts.
When an interrupt is masked off, the mask bit is ‘0’. The interrupt will still post in the interrupt controller. Therefore, clearing
the mask bit only prevents a posted interrupt from becoming a pending interrupt.
For additional information, refer to the
Bit
7
6
5
4
3
2
1
0
PSoC CY8C20x34 TRM, Version 1.0
Individual Register Names and Addresses:
INT_MSK0: 0,E0h
Access : POR
Bit Name
I2C
Sleep
SPI
GPIO
Timer
CapSense
Analog
V Monitor
Name
Interrupt Mask Register 0
RW : 0
I2C
7
RW : 0
Sleep
6
Description
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Register Definitions on page 49
Mask I2C interrupt
Unmask I2C interrupt
Mask sleep interrupt
Unmask sleep interrupt
Mask SPI interrupt
Unmask SPI interrupt
Mask GPIO interrupt
Unmask GPIO interrupt
Mask Timer interrupt
Unmask Timer interrupt
Mask CapSense interrupt
Unmask CapSense interrupt
Mask analog interrupt
Unmask analog interrupt
Mask voltage monitor interrupt
Unmask voltage monitor interrupt
RW : 0
SPI
5
RW : 0
GPIO
4
in the Interrupt Controller chapter.
RW : 0
Timer
3
CapSense
RW : 0
2
0,E0h
RW : 0
Analog
1
INT_MSK0
V Monitor
RW : 0
0,E0h
0
175