CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 126

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

SPI
Status Generation and Interrupts. There are four status
bits in an SPI Block: TX Reg Empty, RX Reg Full, SPI Com-
plete, and Overrun.
TX Reg Empty indicates that a new byte can be written to
the TX Buffer register. When the block is enabled, this status
bit is immediately asserted. This status bit is cleared when
the user writes a byte of data to the TX Buffer register. TX
Reg Empty is a control input to the state machine and, if a
transmission is not already in progress, the assertion of this
control signal initiates one. This is the default SPIM block
interrupt. However, an initial interrupt is not generated when
the block is enabled. The user must write a byte to the TX
Buffer register and that byte must be loaded into the shifter
before interrupts generated from the TX Reg Empty status
bit are enabled.
RX Reg Full is asserted on the edge that captures the eighth
bit of receive data. This status bit is cleared when the user
reads the RX Buffer register (DR2).
126
SS Forced Low
SS
SCLK (Mode 0)
SCLK (Mode 1)
SS Toggled on a Message Basis
SS
SCLK (Mode 0)
SCLK (Mode 1)
SS Toggled on Each Byte
SS
SCLK (Mode 0)
SCLK (Mode 1)
Transfer in Progress
Transfer in Progress
Transfer in Progress
Figure 18-7. SPI Status Timing for Modes 0 and 1
SPI Complete is an optional interrupt and is generated when
eight bits of data and clock have been sent. In modes 0 and
1, this occurs one-half cycle after RX Reg Full is set;
because in these modes, data is latched on the leading
edge of the clock and there is an additional one-half cycle
remaining to complete that clock. In modes 2 and 3, this
occurs at the same edge that the receive data is latched.
This signal may be used to read the received byte or it may
be used by the SPIM to disable the block after data trans-
mission is complete.
Overrun status is set, if RX Reg Full is still asserted from a
previous byte when a new byte is about to be loaded into the
RX Buffer register. Because the RX Buffer register is imple-
mented as a latch, Overrun status is set one-half bit clock
before RX Reg Full status.
See
ships.
Figure 18-7
and
Transfer in Progress
Transfer in Progress
Figure 18-8
PSoC CY8C20x34 TRM, Version 1.0
for status timing relation-