CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 86

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

Comparators
The comparator digital interface performs logic processing
on one or more comparator signals, provides a latching
capability, and routes the result to other chip subsystems.
The comparator signal is routed through a look-up table
(LUT) function. The other input to the LUT is the neighboring
comparator output. The LUT implements 1 of 16 functions
on the two inputs, as selected by the CMP_LUT register.
The LUT output also feeds the set input on an reset/set (RS)
latch. The latch is cleared by writing a ‘0’ to the appropriate
bit in the CMP_RDC register, or by a rising edge from the
other comparator LUT.
12.2
The following registers are only associated with the Comparators in the CY8C20x34 PSoC device and are listed in address
order. For a complete table of the comparator registers, refer to the
Each register description has an associated register table showing the bit structure for that register. Register bits that are
grayed out throughout this document are reserved bits and are not detailed in the register descriptions that follow. Reserved
bits should always be written with a value of ‘0’.
12.2.1
The Comparator Read/Clear Register (CMP_RDC) is used
to read the state of the comparator data signal and the
latched state of the comparator.
Bit 5: CMP1D. Comparator 1 Data State. This bit is a read-
only bit and returns the dynamically changing state of the
comparator.
Bit 4: CMP0D. Comparator 0 Data State. This bit is a read-
only bit and returns the dynamically changing state of the
comparator.
86
0,78h
LEGEND
#
Address
Access is bit specific.
Register Definitions
CMP_RDC
CMP_RDC Register
Name
Bit 7
Bit 6
CMP1D
Bit 5
CMP0D
Bit 4
The primary output for each comparator is the LUT output or
its latched version. These are routed to the CapSense logic
and to the interrupt controller. The comparator LUT output
state and latched state may be directly read by the CPU
through the CMP_RDC register. A selection of comparator
state may also be driven to an output pin.
When disabled, the comparators consume no power. Two
active modes provide a full rail-to-rail input range, or a
somewhat lower power option with limited input range.
Bit 1: CMP1L. Comparator 1 Latched State. This bit is set
and held high whenever the comparator 1 LUT goes high
since the last time this register was read. Refer to the
CRST1 bit in the CMP_CR1 register for information on how
the latch is cleared.
Bit 0: CMP0L. Comparator 0 Latched State. This bit is set
and held high whenever the comparator 0 LUT goes high
since the last time this register was read. Refer to the
CRST0 bit in the CMP_CR1 register for information on how
the latch is cleared.
For additional information, refer to the
on page
“Summary Table of the CapSense Registers” on page
Bit 3
147.
Bit 2
PSoC CY8C20x34 TRM, Version 1.0
CMP1L
Bit 1
CMP0L
CMP_RDC register
Bit 0
Access
# : 00
72.