CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 59

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

This chapter presents the Internal Main Oscillator (IMO) and its associated register. The IMO produces clock signals of 6 MHz
and 12 MHz. For a quick reference of all PSoC registers in address order, refer to the
page
7.1
The Internal Main Oscillator (IMO) outputs two clocks: a
SYSCLK (that can be the internal 6/12 MHz clock or an
external clock) and a 12/24 MHz clock called SYSCLKx2
that runs at twice the SYSCLK frequency. In the absence of
a high-precision input source from a crystal oscillator, the
accuracy of the internal 6/12 MHz clocks will be ±5% over
temperature and voltage (2.7V to 3.6V) variation. No exter-
nal components are required to achieve this level of accu-
racy.
The IMO can be disabled when using an external clocking
source. Registers for controlling these operations are found
in the
Lower frequency SYSCLK settings are available by setting
the Slow IMO (SLIMO) bit in the CPU_SCR1 register. With
this bit set and the corresponding factory trim value applied
to the IMO_TR register, SYSCLK can be lowered to 6 MHz.
This offers lower device power consumption for systems
that can operate with the reduced system clock. Slow IMO
mode is discussed further in the
page
PSoC CY8C20x34 TRM, Version 1.0
7.
139.
59.
Digital Clocks chapter on page
Architectural Description
Internal Main Oscillator (IMO)
“Application Overview” on
91.
7.2
To save power, the IMO frequency can be reduced from 12
MHz to 6 MHz using the SLIMO bit in the CPU_SCR1 regis-
ter, in conjunction with the Trim values in the IMO_TR regis-
ter. Both methods are described below.
7.2.1
An 8-bit register (IMO_TR) is used to trim the IMO. Bit 0 is
the LSB and bit 7 is the MSB. The trim step size is approxi-
mately 80 kHz.
A factory trim setting is loaded into the IMO_TR register at
boot time for 2.7V to 3.6V operation. For operation in the
voltage ranges below 2.7V, user code must modify the con-
tents of this register with values stored in Flash bank 0 as
shown in
Read command to the Supervisory ROM.
7.2.2
Forcing the CPU_SCR1 register bit 4 high engages the
Slow IMO feature. The IMO will immediately drop to a lower
frequency. Factory trim settings are stored in Flash bank 0
as shown in
frequency combinations.
Table 7-1. Slow IMO
A TableRead command to the Supervisory ROM is per-
formed to set the IMO to the different frequencies. See the
“TableRead Function” on page
2.7V to 3.6V
Voltage
Table 4-11 on page
Application Overview
Table 4-11 on page 43
Trimming the IMO
Engaging Slow IMO
Normal IMO
Frequency
Register Reference chapter on
12 MHz
43. This is done with a Table
43.
for the following voltage/
Frequency
Slow IMO
6 MHz
59