CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 123

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

18.3
18.3.1
Figure 18-3
defined as 0,1, 2, or 3. These mode numbers are an encod-
ing of two control bits: Clock Phase and Clock Polarity.
Clock phase indicates the relationship of the clock to the
data. When the clock phase is '0', it means that the data is
registered as an input on the leading edge of the clock and
PSoC CY8C20x34 TRM, Version 1.0
Timing Diagrams
shows the SPI modes which are typically
SPI Mode Timing
SCLK, Polarity=0 (Mode 0)
SCLK, Polarity=1 (Mode 1)
SCLK, Polarity=0 (Mode 2)
SCLK, Polarity=1 (Mode 3)
MOSI
MISO
MOSI
MISO
SS_
SS_
MODE 0, 1 (Phase=0) Input on leading edge. Output on trailing edge.
MODE 2, 3 (Phase=1) Output on leading edge. Input on trailing edge.
Figure 18-3. SPI Mode Timing
7
7
6
6
5
the next data is output on the trailing edge of the clock.
When the clock phase is '1', it means that the next data is
output on the leading edge of the clock and that data is reg-
istered as an input on the trailing edge of the clock.
Clock polarity controls clock inversion. When clock polarity
is set to '1’, the clock idle state is high.
5
4
4
3
3
2
2
1
1
0
0
123
SPI