CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 125

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

Normal Operation. Typical timing for a SPIM transfer is
shown in
writes a byte to transmit when TX Reg Empty status is true.
If no transmission is currently in progress, the data is loaded
into the shifter and the transmission is initiated. The TX Reg
Empty status is asserted again and the user is allowed to
write the next byte to be transmitted to the TX Buffer regis-
PSoC CY8C20x34 TRM, Version 1.0
Figure 18-5
INTERNAL CLOCK
clock is CLK input
INTERNAL CLOCK
clock is CLK input
internal bit rate
divided by two.
Free running,
TX REG EMPTY
internal bit rate
divided by two.
SCLK (MODE 0)
SCLK (MODE 1)
Free running,
TX REG EMPTY
SCLK (MODE 2)
SCLK (MODE 3)
RX REG FULL
RX REG FULL
CLK INPUT
and
CLK INPUT
User writes first
Buffer register.
byte to the TX
Figure
User writes first
Buffer register.
byte to the TX
MOSI
MOSI
18-6. The user initially
Figure 18-5. Typical SPIM Timing in Mode 0 and 1
Figure 18-6. Typical SPIM Timing in Mode 2 and 3
Buffer write.
Buffer write.
Setup time
Setup time
for the TX
for TX
First input bit
is latched.
First input bit
is latched.
D7
with the first byte.
D7
Shifter is loaded
Shifter is loaded
with first byte.
First shift
First shift
D6
D6
ter. After the last bit is output, if TX Buffer data is available
with one-half clock setup time to the next clock, a new byte
transmission will be initiated. A SPIM block receives a byte
at the same time that it sends one. The SPI Complete or RX
Reg Full can be used to determine when the input byte has
been received.
User writes next
Buffer register.
D5
byte to the TX
D5
User writes next
Buffer register.
byte to the TX
edge and is latched
data is valid on this
Last bit of received
edge and is latched
data is valid on this
Last bit of received
into RX Buffer.
into RX Buffer.
D2
D2
D1
D1
D0
D0
Shifter is loaded
with next byte.
Shifter is loaded
with the next
D7
byte.
D7
125
SPI