CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 49

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

5.3
These registers are associated with the Interrupt Controller and are listed in address order. The register descriptions have an
associated register table showing the bit structure for that register. The grayed out bits in the tables are reserved bits and are
not detailed in the register descriptions that follow. Always write reserved bits with a value of ‘0’. For a complete table of Inter-
rupt Controller registers, refer to the
5.3.1
The Interrupt Clear Register 0 (INT_CLR0) is used to enable
the individual interrupt sources’ ability to clear posted inter-
rupts.
The INT_CLR0 register is similar to the INT_MSK0 register
in that it holds a bit for each interrupt source. Functionally
the INT_CLR0 register is similar to the INT_VC register,
although its operation is completely independent. When the
INT_CLR0 register is read, any bits that are set indicates an
interrupt has been posted for that hardware resource.
Therefore, reading this register gives the user the ability to
determine all posted interrupts.
The Enable Software Interrupt (ENSWINT) bit in the
INT_SW_EN register determines the way an individual bit
value, written to an INT_CLR0 register, is interpreted. When
ENSWINT is cleared (the default state), writing 1's to the
INT_CLR0 register has no effect. However, writing 0's to the
INT_CLR0 register, when ENSWINT is cleared, will cause
the corresponding interrupt to clear. If the ENSWINT bit is
set, any 0's written to the INT_CLR0 register is ignored.
However, 1's written to the INT_CLR0 register, while
ENSWINT is set, will cause an interrupt to post for the corre-
sponding interrupt.
Software interrupts can aid in debugging interrupt service
routines by eliminating the need to create system level inter-
actions that are sometimes necessary to create a hardware-
only interrupt.
PSoC CY8C20x34 TRM, Version 1.0
0,DAh
Address
Register Definitions
INT_CLR0
INT_CLR0 Registers
Name
Bit 7
I2C
“Summary Table of the Core Registers” on page
Sleep
Bit 6
Bit 5
SPI
GPIO
Bit 4
Bit 7: I2C. This bit allows posted I2C interrupts to be read,
cleared, or set.
Bit 6: Sleep. This bit allows posted sleep interrupts to be
read, cleared, or set.
Bit 5: SPI. This bit allows posted SPI interrupts to be read,
cleared, or set.
Bit 4: GPIO. This bit allows posted GPIO interrupts to be
read, cleared, or set.
Bit 3: Timer. This bit allows posted Timer interrupts to be
read, cleared, or set.
Bit 2: CapSense. This bit allows posted CapSense inter-
rupts to be read, cleared, or set.
Bit 1: Analog. This bit allows posted analog interrupts to
be read, cleared, or set.
Bit 0: V Monitor. This bit allows posted voltage monitor
interrupts to be read, cleared, or set.
For additional information, refer to the
page
173.
Timer
Bit 3
CapSense
Bit 2
24.
Analog
Bit 1
INT_CLR0 register on
Interrupt Controller
V Monitor
Bit 0
RW : 00
Access
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