CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 188

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

OUT_P1
20.4.6
This register enables specific internal signals to be output to Port 1 pins.
Note that the GPIO drive modes must be specified to support the desired output mode (registers PRT1DM1 and PRT1DM0).
If a pin is enabled for output by a bit in this register, the corresponding signal has priority over any other internal function that
may be configured to output to that pin.
For additional information, refer to the
Bit
7
6
5
4
3
2
1
0
188
Individual Register Names and Addresses:
OUT_P1: 1,DDh
Access : POR
Bit Name
1,DDh
P16D
P16EN
P14D
P14EN
P12D
P12EN
P10D
P10EN
Name
OUT_P1
Output Override to Port 1 Register
RW : 0
P16D
7
P16EN
RW : 0
6
Description
Bit selects the data output to P1[6] when P16EN is high.
1
0
1
Bit enables pin P1[6] for output of the signal selected by the P16D bit.
0
1
Bit selects the data output to P1[4] when P14EN is high.
0
1
Bit enables pin P1[4] for output of the signal selected by the P14D bit.
0
1
Bit selects the data output to P1[2] when P12EN is high.
0
Bit enables pin P1[2] for output of the signal selected by the P12D bit.
0
1
Bit selects the data output to P1[0] when P10EN is high.
0
1
Bit enables pin P1[0] for output of the signal selected by the P10D bit.
0
1
Register Definitions on page 94
Select Timer output (TIMEROUT)
Select CLK32
No internal signal output to P1[6]
Output the signal selected by P16D to P1[6]
Select Relaxation Oscillator (RO)
Select Comparator 1 Output (CMP1)
No internal signal output to P1[4]
Output the signal selected by P14D to P1[4]
Select Main System Clock (SYSCLK)
Select CapSense output signal (CS). This signal is selected by the CSOUT[1:0] bits in the
CS_CR0 register.
No internal signal output to P1[2]
Output the signal selected by P12D to P1[2]
Select Sleep Interrupt (SLPINT)
Select Comparator 0 Output (CMP0)
No internal signal output to P1[0]
Output the signal selected by P10D to P1[0]
RW : 0
P14D
5
RW : 0
P14EN
4
in the Digital Clocks chapter.
RW : 0
P12D
3
P12EN
RW : 0
PSoC CY8C20x34 TRM, Version 1.0
2
1,DDh
RW : 0
P10D
1
P10EN
RW : 0
0