CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 90

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

Section D: System Resources
System Resources Register Summary
The table below lists all the PSoC registers for the system resources, in address order, within their system resource configu-
ration. The bits that are grayed out are reserved bits. If these bits are written, they should always be written with a value of ‘0’.
Summary Table of the System Resource Registers
90
1,DDh
1,E0h
1,E2h
0,D6h
0,D7h
0,D8h
1,EAh
0,FEh
0,FFh
1,E3h
1,E4h
0,29h
0,2Ah
0,2Bh
1,29h
0,B0h
0,B1h
0,B2h
LEGEND
X
R
W Write register or bit(s).
#
Address
The value after power on reset is unknown.
Read register or bit(s).
Access is bit specific. Refer to the Register Details chapter for additional information.
OUT_P1
OSC_CR0
OSC_CR2
I2C_CFG
I2C_SCR
I2C_DR
BDG_TR
CPU_SCR1
CPU_SCR0
VLT_CR
VLT_CMP
SPI_TXR
SPI_RXR
SPI_CR
SPI_CFG
PT_CFG
PT_DATA1
PT_DATA0
Name
Bus Error
LSb First
IRESS
P16D
GIES
Bit 7
Disable Buzz
Clock Sel
Overrun
PSelect
TC[2:0]
P16EN
Bit 6
INTERNAL VOLTAGE REFERENCES REGISTER (page 108)
PROGRAMMABLE TIMER REGISTERS (page 133)
SYSTEM RESET REGISTERS (page 110)
DIGITAL CLOCK REGISTERS (page 94)
Complete
No Buzz
I2C SLAVE REGISTERS (page 100)
WDRS
Status
P14D
Bit 5
Stop
SPI
POR REGISTERS (page 115)
SPI REGISTERS (page 119)
PORLEV[1:0]
TX Reg
P14EN
Stop IE
Bypass
SLIMO
PORS
Empty
Bit 4
ACK
Sleep[1:0]
Data[7:0]
Data[7:0]
Data[7:0]
Data[7:0]
RX Reg Full
LVDTBEN
Address
NoWrite
P12D
Sleep
Bit 3
SS_
Clock Rate[1:0]
Clock Phase
EXTCLKEN
Data[4:0]
Transmit
SS_EN_
P12EN
V[4:0]
Bit 2
PSoC CY8C20x34 TRM, Version 1.0
CPU Speed[2:0]
One Shot
IMODIS
VM[2:0]
Polarity
Int Sel
P10D
Clock
Bit 1
LRB
LVD
Complete
IRAMDIS
P10EN
START
Enable
Enable
PPOR
STOP
Slave
Bit 0
Byte
RW : 00
RW : 01
RW : 00
RW : 00
RW : 00
RW : 50
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
Access
W : 00
R : 00
# : XX
R : 00
R : 00
# : 00
# : 00