CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 57

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

6.2
The following registers are associated with the General Purpose IO (GPIO) and are listed in address order. The register
descriptions have an associated register table showing the bit structure for that register. The bits in the tables that are grayed
out are reserved bits and are not detailed in the register descriptions that follow. Reserved bits should always be written with
a value of ‘0’. For a complete table of GPIO registers, refer to the
For a selected GPIO block, the individual registers are addressed in the
In the register names, the ‘x’ is the port number, configured at the PSoC device level (x = 0 to 7 typically). All register values
are readable, except for the PRTxDR register; reads of this register return the pin state instead of the register bit state.
6.2.1
The Port Data Register (PRTxDR) allows for write or read
access of the current logical equivalent of the voltage on the
pin.
Bits 7 to 0: Data[7:0]. Writing the PRTxDR register bits set
the output drive state for the pin to high (for Data = 1) or low
(Data = 0), unless a bypass mode is selected (see
Bypass” on page
6.2.2
The Port Interrupt Enable Register (PRTxIE) is used to
enable/disable interrupts from individual GPIO pins.
Bits 7 to 0: Interrupt Enables[7:0]. A ‘1’ enables the INTO
output at the block and a ‘0’ disables INTO so it is only High-
Z. In the enabled state, the type of GPIO edge that actually
PSoC CY8C20x34 TRM, Version 1.0
0,xxh
LEGEND
xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers,
0,xxh
LEGEND
xx An “x” after the comma in the address field indicates that there are multiple instances of the register. For an expanded address listing of these registers,
Address
Address
refer to the
refer to the
Register Definitions
PRTxDR
PRTxIE
“Core Register Summary” on page
“Core Register Summary” on page
PRTxDR Registers
PRTxIE Registers
Name
Name
56).
Bit 7
Bit 7
Bit 6
Bit 6
24.
24.
Bit 5
Bit 5
“Data
Interrupt Enables[7:0]
Bit 4
Bit 4
Data[7:0]
Reading the PRTxDR register returns the actual pin state,
as seen by the input buffer. This may not be the same as the
expected output state, if the load pulls the pin more strongly
than the pin’s configured output drive. See
page 54
For additional information, refer to the
page
causes an interrupt is set by the IOINT bit in the IO_CFG
register.
For additional information, refer to the
page
“Summary Table of the Core Registers” on page
140.
141.
Bit 3
Bit 3
“Summary Table of the Core Registers” on page
for a detailed discussion of digital IO.
Bit 2
Bit 2
Bit 1
Bit 1
General Purpose IO (GPIO)
PRTxDR register on
PRTxIE register on
Bit 0
Bit 0
“Digital IO” on
24.
RW : 00
RW : 00
Access
Access
24.
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