CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 153

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

20.3.13 CS_CR0
This register controls the operation of the CapSense counters.
Bits [7:1] should never be written to while the block is enabled.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits should always be written with a value of ‘0’. For additional information, refer to the
76
Bit
7:6
2:1
0
PSoC CY8C20x34 TRM, Version 1.0
Individual Register Names and Addresses:
CS_CR0 : 0,A0h
Access : POR
Bit Name
in the CapSense Module chapter .
CSOUT[1:0]
MODE[1:0]
EN
Name
CapSense Control Register 0
7
CSOUT[1:0]
RW : 0
6
Description
CapSense Output
00b
01b
10b
11b
CapSense Counter Mode
00b
01b
10b
11b
0
1
Selected Input
CapSense Interrupt
Carry Out Low Byte
Carry Out High Byte
Event mode. Start in Enable, stop on interrupt event.
Pulse Width mode. Start on positive edge of next input. Stop on negative edge of input.
Period mode. Start on positive edge of input. Stop on next positive edge of input.
Start in Enable, continuous operation until disable.
Counting is stopped and all counter values are reset to ‘0’.
Counters are enabled for counting.
5
4
3
2
MODE[1:0]
RW : 0
Register Definitions on page
1
0,A0h
RW : 0
0,A0h
CS_CR0
EN
0
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