CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 79

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

10.2.7
The CapSense Status Register (CS_STAT) controls
CapSense counter options.
Status Bits 7 to 4 – The posted CapSense interrupts are
the corresponding status bits in this register. Interrupt clear-
ing is performed by clearing the associated status bit. Status
can only be updated while the block is enabled and running.
All status bits are cleared when the block is disabled.
Bit 7: INS. Input Status. Reading a ‘1’ indicates a rising
edge on the selected input was detected. Reading a ‘0’ indi-
cates that this event did not occur. This bit is cleared by writ-
ing a ‘0’ to this bit position. Writing a ‘1’ has no effect.
Bit 6: COLS. Counter Carry Out Low Status. Reading a ‘1’
indicates an overflow occurred in the Counter Low block.
Reading a ‘0’ indicates that this event did not occur. This bit
is cleared by writing a ‘0’ to this bit position. Writing a ‘1’ has
no effect.
Bit 5: COHS. Counter Carry Out High Status. Reading a ‘1’
indicates an overflow occurred in the Counter High block.
Reading a ‘0’ indicates that this event did not occur. This bit
is cleared by writing a ‘0’ to this bit position. Writing a ‘1’ has
no effect.
Bit 4: PPS. Pulse Width/Period Status. Reading a ‘1’ indi-
cates the completion of a pulse width or period measure-
ment (as defined by the MODE[1:0] bits in CS_CR0). This
10.2.8
The CapSense Timer Register (CS_TIMER) sets the timer
count value.
PSoC CY8C20x34 TRM, Version 1.0
0,A6h
LEGEND
#
0,A7h
Address
Address
Access is bit specific.
CS_STAT
CS_TIMER
CS_STAT Register
CS_TIMER Register
Name
Name
Bit 7
Bit 7
INS
COLS
Bit 6
Bit 6
COHS
Bit 5
Bit 5
Bit 4
Bit 4
PPS
bit is cleared by writing a ‘0’ to this bit position. Writing a ‘1’
has no effect.
Mask Bits 3 to 0 – The interrupt mask bits should never be
modified while the block is enabled. If modification to bits 3
to 0 is necessary while the block is enabled, then special
attention must be paid to ensure that the status bits, bits 7 to
4, are not accidentally cleared. This can be done by writing a
‘1’ to all of the status bits when writing to the mask bits.
Bit 3: INM. Input Interrupt Mask. When this bit is a ‘1’, a ris-
ing edge event on the input will assert the block interrupt.
When this bit is a ‘0’, this event is masked.
Bit 2: COLM. Counter Carry Out Low Mask. When this bit
is a ‘1’, a carry out from the counter low block will assert the
block interrupt. When this bit is a ‘0’, this event is masked.
Bit 1: COHM. Counter Carry Out High Mask. When this bit
is a ‘1’, a carry out from the counter high block will assert the
block interrupt. When this bit is a ‘0’, this event is masked.
Bit 0: PPM. Pulse Width/Period Mask When this bit is a ‘1’,
the completion of a pulse width or period measurement will
assert the block interrupt. When this bit is a ‘0’, this event is
masked.
For additional information, refer to the
page
Bits 5 to 0: Timer Count Value[5:0]. The 6-bit value in this
register sets the initial count value for the timer.
For additional information, refer to the
on page
Timer Count Value[5:0]
159.
Bit 3
Bit 3
INM
160.
COLM
Bit 2
Bit 2
COHM
Bit 1
Bit 1
CS_STAT register on
CS_TIMER register
Bit 0
PPM
Bit 0
CapSense Module
RW : 00
Access
Access
# : 00
79