CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 112

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

System Resets
16.4
16.4.1
A Power on Reset (POR) is triggered whenever the supply
voltage is below the POR trip point. POR ends once the sup-
ply voltage rises above this voltage. Refer to the
LVD chapter on page 115
tion of the POR block.
POR consists of two pieces: an imprecise POR (IPOR) and
a Precision POR (PPOR). “POR” refers to the OR of these
two functions. IPOR has coarser accuracy and its trip point
is typically lower than PPOR’s trip point. PPOR is derived
from a circuit that is calibrated (during boot) for a very accu-
rate location of the POR trip point.
During POR (POR=1), the IMO is powered off for low power
during start-up. Once POR de-asserts, the IMO is started
(see
POR configures register reset status bits as shown in
Table 16-1 on page
Gap Trim register (BDG_TR), but IPOR does reset this reg-
ister.
16.4.2
An External Reset (XRES) is caused by pulling the XRES
pin high. The XRES pin has an always-on, pull down resis-
tor, so it does not require an external pull down for operation
and can be tied directly to ground or left open. Behavior after
XRES is similar to POR.
112
Figure
Timing Diagrams
16-4).
Power On Reset
External Reset
114. PPOR does not affect the Band-
IMO (not to scale)
IMO (not to scale)
for more information on the opera-
Sleep Timer
Sleep Timer
WDR: Reset 1 cycle, then one additional cycle before the CPU reset is released.
IRES: Reset 1 cycle, then 2048 additional cycles low power hold-off, and then 1
cycle with IMO on before the CPU reset is released.
CPU Reset
CPU Reset
IMO PD
IMO PD
CLK32
CLK32
Reset
Reset
Figure 16-3. Key Signals During WDR and IRES
(Stays low)
0
0
POR and
During XRES (XRES=1), the IMO is powered off for low
power during start-up. Once XRES de-asserts, the IMO is
started (see
How the XRES configures register reset status bits is shown
in
16.4.3
The user has the option to enable the Watchdog Timer
Reset (WDR), by clearing the PORS bit in the CPU_SCR0
register. Once the PORS bit is cleared, the watchdog timer
cannot be disabled. The only exception to this is if a POR/
XRES event takes place which will disable the WDR. Note
that a WDR does not clear the Watchdog timer. See
dog Timer” on page 68
tion.
When the watchdog timer expires, a watchdog event occurs
resulting in the reset sequence. Some characteristics
unique to the WDR are as follows.
n
n
n
How the WDR configures register reset status bits is shown
in
1
1
Table 16-1 on page
Table 16-1 on page
PSoC device reset asserts for one cycle of the CLK32K
clock (at its reset state).
The IMO is not halted during or after WDR (that is, the
part does not go through a low power phase).
CPU operation re-starts one CLK32K cycle after the
internal reset de-asserts (see
2
2
Figure
Watchdog Timer Reset
N=2048
16-4).
114.
114.
PSoC CY8C20x34 TRM, Version 1.0
for details of the Watchdog opera-
Figure
16-3).
“Watch-