CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 87

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

12.2.2
The Comparator Multiplexer Register (CMP_MUX) contains
control bits for input selection of comparators 0 and 1.
Bits 7 and 6: INP1[1:0]. These bits select the positive input
data source for comparator 1. The selections are shown in
the table.
Bits 5 and 4: INN1[1:0]. These bits select the negative
input data source for comparator 1. The selections are
shown in the table.
Bits 3 and 2: INP0[1:0]. These bits select the positive input
data source for comparator 0. The selections are shown in
the table.
12.2.3
The Comparator Control Register 0 (CMP_CR0) is used to
enable and configure the input range of the comparators.
Bit 5: CMP1R. This bit selects the input range for compara-
tor 1. Setting the bit high selects a somewhat lower power
mode that does not operate rail-to-rail.
Bit 4: CMP1EN. This bit enables comparator 1.
PSoC CY8C20x34 TRM, Version 1.0
0,79h
0,7Ah
Address
Address
CMP_MUX
CMP_CR0
CMP_MUX Register
CMP_CR0 Register
Name
Name
Bit 7
Bit 7
INP1[1:0]
Bit 6
Bit 6
CMP1R
Bit 5
Bit 5
INN1[1:0]
CMP1EN
Bit 4
Bit 4
Bits 1 and 0: INN0[1:0]. These bits select the negative
input data source for comparator 0. The selections are
shown in the table below.
For additional information, refer to the
on page
Bit 1: CMP0R. This bit selects the input range for compara-
tor 1. Setting the bit high selects a somewhat lower power
mode that does not operate rail-to-rail.
Bit 0: CMP0EN. This bit enables comparator 0.
For additional information, refer to the
page
00
01
10
11
149.
Analog Global Bus (Mix-ups
Reserved
P0[1] pad
P0[3] pad
Bit 3
Bit 3
148.
INP0[1:0]
INPx[1:0]
Bit 2
Bit 2
CMP0R
Bit 1
Bit 1
00
01
10
11
INN0[1:0]
1.3V Reference
RefLo Reference
Reserved
RefHi Reference
CMP_CR0 register on
CMP0EN
CMP_MUX register
Bit 0
Bit 0
INNx[1:0]
Comparators
RW : 00
RW : 00
Access
Access
87