CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 155

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

20.3.15 CS_CR2
This register contains additional CapSense system control options.
For additional information, refer to the
Bit
7:6
5
4
2
0
PSoC CY8C20x34 TRM, Version 1.0
Individual Register Names and Addresses:
CS_CR2 : 0,A2h
Access : POR
Bit Name
IRANGE
IDACDIR
IDAC_EN
PXD_EN
RO_EN
Name
CapSense Control Register 2
7
IRANGE
RW : 0
6
Description
Bits scale the IDAC current output. The IDAC_D register sets the base current in the IDAC.
00
01
10
11
Bit determines the source/sink state of the IDAC when enabled (IDAC_EN = 1 or PXD_EN = 1).
0
1
Bit provides manual connection of the IDAC to the analog global bus. The IDAC is automatically con-
nected when RO_EN = 1 or PXD_EN = 1.
0
1
0
1
0
1
Register Definitions on page 76
IDAC output scaled to 1X range.
IDAC output scaled to 2X range.
IDAC output scaled to 4X range.
IDAC output scaled to 8X range.
IDAC sources current to analog global bus.
IDAC sinks current from analog global bus.
No manual connection
IDAC is connected to analog global bus.
No clock to I/O pins
Enabled pins switch between ground and the analog global bus. Clock rate selected by the
CLKSEL bits in the CS_CR1 register. Selected clock drives CapSense timer.
Relaxation oscillator disabled.
Relaxation oscillator enabled. Charging currents are set by the IRANGE bits and the
IDAC_D register value.
IDACDIR
RW : 0
5
IDAC_EN
RW : 0
4
in the CapSense Module chapter .
3
PXD_EN
RW : 0
2
1
0,A2h
RO_EN
RW : 0
0,A2h
CS_CR2
0
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