CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 171

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

20.3.31 I2C_SCR
This register is used by the slave to control the flow of data bytes and to keep track of the bus state during a transfer.
Bits in this register are held in reset until one of the enable bits in I2C_CFG is set.
In the table above, note that reserved bits are grayed table cells and are not described in the bit description section below.
Reserved bits should always be written with a value of ‘0’. For additional information, refer to the
100
Bit
7
5
4
3
2
1
0
PSoC CY8C20x34 TRM, Version 1.0
Individual Register Names and Addresses:
I2C_SCR: 0,D7h
Access : POR
Bit Name
in the I2C Slave chapter .
Bus Error
Stop Status
ACK
Address
Transmit
LRB
Byte Complete
Name
I
2
Bus Error
C Status and Control Register
RC : 0
7
6
Description
0
1
0
1
Acknowledge Out. Bit is automatically cleared by hardware on a Byte Complete event.
0
1
0
1
Bit is set by firmware to define the direction of the byte transfer. Any Start detect or a write to the Start
or Restart generate bits, when operating in Master mode, will also clear the bit.
0
1
Last Received Bit. The value of the 9
the receiver. Any Start detect or a write to the Start or Restart generate bits, when operating in Master
mode, will also clear the bit.
0
1
Transmit/Receive Mode:
0
Transmit Mode:
1
Receive Mode:
1
Status bit. It must be cleared by firmware by writing a ‘0’ to the bit position. It is never
cleared by the hardware.
A misplaced Start or Stop condition was detected.
Status bit. It must be cleared by firmware with write of ‘0’ to the bit position. It is never
cleared by the hardware.
A Stop condition was detected.
NACK the last received byte.
ACK the last received byte
Status bit. It must be cleared by firmware with write of ‘0’ to the bit position.
The received byte is a slave address.
Receive mode
Transmit mode
Last transmitted byte was ACK’ed by the receiver.
Last transmitted byte was NACK’ed by the receiver.
No completed transmit/receive since last cleared by firmware. Any Start detect or a write to
the Start or Restart generate bits, when operating in Master mode, will also clear the bit.
Eight bits of data have been transmitted and an ACK or NACK has been received.
Eight bits of data have been received.
Stop Status
RC : 0
5
RW : 0
ACK
4
th
bit in a Transmit sequence, which is the acknowledge bit from
Address
RC : 0
3
Transmit
RW : 0
2
0,D7h
Register Definitions on page
RC : 0
LRB
1
Byte Complete
RC : 0
0,D7h
I2C_SCR
0
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