CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 88

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

Comparators
12.2.4
The Comparator Control Register 1 (CMP_CR1) is used to
configure the comparator output options.
Bit 7: CINT1. This bit connects the comparator 1 output to
the analog output.
Bit 6: CPIN1. This bit selects whether the comparator 1
LUT output or the latched output can be routed to a GPIO
pin.
Bit 5: CRST1. This bit selects whether the comparator 1
latch is reset on register write or by a rising edge from the
comparator 0 LUT output.
Bit 4: CDS1. This bit selects between the comparator 1
LUT and the latched output, for the main comparator output,
that drives to the capacitive sense and interrupt logic.
12.2.5
The Comparator LUT Control Register (CMP_LUT) is used
to select the logic function.
Bits 7 to 4: LUT1[3:0]. These bits control the selection of
the LUT 1 logic functions that may be selected for the com-
parator channel 1.
Bits 3 to 0: LUT0[3:0]. These bits control the selection of
LUT 0 logic functions that may be selected for the compara-
tor channel 0.
88
0,7Bh
0,7Ch
Address
Address
CMP_CR1
CMP_LUT
CMP_CR1 Register
CMP_LUT Register
Name
Name
CINT1
Bit 7
Bit 7
CPIN1
Bit 6
Bit 6
LUT1[3:0]
CRST1
Bit 5
Bit 5
CDS1
Bit 4
Bit 4
Bit 3: CINT0. This bit connects the comparator 0 output to
the analog output.
Bit 2: CPIN0. This bit selects whether the comparator 0
LUT output or the latched output can be routed to a GPIO
pin.
Bit 1: CRST0. This bit selects whether the comparator 0
latch is reset on register write or by a rising edge from the
comparator 1 LUT output.
Bit 0: CDS0. This bit selects between the comparator 0
LUT and the latched output, for the main comparator output,
that drives to the capacitive sense and interrupt logic.
For additional information, refer to the
page
Table 12-1. Logic Function Selection
For additional information, refer to the
page
CLUTx[3:0]
150.
152.
CINT0
Bit 3
Bit 3
0h: 0000: FALSE
1h: 0001: A .AND. B
2h: 0010: A .AND. B
3h: 0011: A
4h: 0100: A .AND. B
5h: 0101: B
6h: 0110: A .XOR. B
7h: 0111: A .OR. B
8h: 1000: A .NOR. B
9h: 1001: A .XNOR. B
Ah: 1010: B
Bh: 1011: A .OR. B
Ch: 1100: A
Dh: 1101: A .OR. B
Eh: 1110: A. NAND. B
Fh: 1111: TRUE
CPIN0
Bit 2
Bit 2
LUT0[3:0]
PSoC CY8C20x34 TRM, Version 1.0
CRST0
Bit 1
Bit 1
CMP_CR1 register on
CMP_LUT register on
CDS0
Bit 0
Bit 0
Access
RW : 00
Access
RW : 00