CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 63

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

This chapter discusses the Sleep and Watchdog operations and their associated registers. For a complete table of the Sleep
and Watchdog registers, refer to the
registers in address order, refer to the
9.1
Device components that are involved in Sleep and Watch-
dog operation are the selected 32 kHz clock, the sleep timer,
the Sleep bit in the CPU_SCR0 register, the sleep circuit (to
sequence going into and coming out of sleep), the bandgap
refresh circuit (to periodically refresh the reference voltage
during sleep), and the watchdog timer.
The goal of Sleep operation is to reduce average power
consumption as much as possible. The system has a sleep
state that can be initiated under firmware control. In this
state, the CPU is stopped at an instruction boundary and the
6/12 MHz oscillator (IMO), the Flash memory module, and
bandgap voltage reference are powered down. The only
blocks that remain in operation are the 32 kHz oscillator,
PSoC blocks clocked from the 32 kHz clock selection, and
the supply voltage monitor circuit.
The system can only wake up from sleep as a result of an
interrupt or reset event. The sleep timer can provide periodic
interrupts to allow the system to wake up, poll peripherals,
or do real-time functions, and then go to sleep again. The
GPIO (pin) interrupt, supply monitor interrupt, and analog
interrupt are examples of asynchronous interrupts that can
also be used to wake the system up.
The Watchdog Timer (WDT) circuit is designed to assert a
hardware reset to the device after a pre-programmed inter-
val, unless it is periodically serviced in firmware. In the event
that an unexpected execution path is taken through the
code, this functionality serves to reboot the system. It can
also restart the system from the CPU halt state.
Once the WDT is enabled, it can only be disabled by an
External Reset (XRES) or a Power On Reset (POR). A WDT
reset will leave the WDT enabled. Therefore, if the WDT is
used in an application, all code (including initialization code)
must be written as though the WDT is enabled.
PSoC CY8C20x34 TRM, Version 1.0
9.
Architectural Description
Sleep and Watchdog
“Summary Table of the Core Registers” on page
Register Reference chapter on page
9.1.1
The Sleep Timer is a 15-bit up counter clocked by the 32
kHz clock source. This timer is always enabled. The excep-
tion to this is within an ICE (in-circuit emulator) in debugger
mode and when the Stop bit in the CPU_SCR0 is set; the
sleep timer is disabled, so that the user will not get continual
watchdog resets when a breakpoint is hit in the debugger
environment.
If the associated sleep timer interrupt is enabled, a periodic
interrupt to the CPU is generated based on the sleep inter-
val selected from the OSC_CR0 register. The sleep timer
functionality does not need to be directly associated with the
sleep state. It can be used as a general purpose timer inter-
rupt regardless of sleep state.
The reset state of the sleep timer is a count value of all
zeros. There are two ways to reset the sleep timer. Any
hardware reset, (that is, POR, XRES, or Watchdog Reset
(WDR) will reset the sleep timer. There is also a method that
allows the user to reset the sleep timer in firmware. A write
of 38h to the RES_WDT register clears the sleep timer.
Note Any write to the RES_WDT register also clears the
watchdog timer.
Clearing the sleep timer may be done at anytime to synchro-
nize the sleep timer operation to CPU processing. A good
example of this is after POR. The CPU hold-off, due to volt-
age ramp and others, may be significant. In addition, a sig-
nificant amount of program initialization may be required.
However, the sleep timer starts counting immediately after
POR and will be at an arbitrary count when user code
begins execution. In this case, it may be desirable to clear
the sleep timer before enabling the sleep interrupt initially to
ensure that the first sleep period is a full interval.
139.
Sleep Timer
24. For a quick reference of all PSoC
63