CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 84

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

IO Analog Multiplexer
11.3
The following registers are only associated with the Analog Bus Mux in the CY8C20x34 PSoC device and are listed in
address order. For a complete table of the IO Analog Multiplexer registers, refer to the
isters” on page
ister bits that are grayed out throughout this document are reserved bits and are not detailed in the register descriptions that
follow. Reserved bits should always be written with a value of ‘0’.
11.3.1
The Analog Mux Configuration Register (AMUX_CFG) is
used to configure the integration capacitor pin connections
to the analog global bus.
Bits 3 and 2: ICAPEN[1:0]. Setting these bits connect an
internal capacitor (up to approximately 100 pF) to the analog
global bus.
11.3.2
The Analog Mux Port Bit Enable Registers (MUX_CR0,
MUX_CR1, MUX_CR2, and MUX_CR3) are used to control
the connection between the analog mux bus and the corre-
sponding pin.
84
0,61h
1,D8h
1,D9h
1,DAh
1,DBh
Address
Address
AMUX_CFG
MUX_CR0
MUX_CR1
MUX_CR2
MUX_CR3
Register Definitions
AMUX_CFG Register
MUX_CRx Registers
Name
Name
72. Each register description has an associated register table showing the bit structure for that register. Reg-
Bit 7
Bit 7
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
ENABLE[7:0]
ENABLE[7:0]
ENABLE[7:0]
ENABLE[7:0]
Bits 1 and 0: INTCAP[1:0]. These bits are used to choose
between the P0[1] and P0[3] pins for the integration capaci-
tor for charge integration capacitive sensing.
For additional information, refer to the
on page
Bits 7 to 0: ENABLE[7:0]. The bits in these registers
enable connection of individual pins to the analog mux bus.
Each IO port has a corresponding MUX_CRx register.
For additional information, refer to the
page
186.
Bit 3
Bit 3
145.
ICAPEN[1:0]
Bit 2
Bit 2
“Summary Table of the CapSense Reg-
PSoC CY8C20x34 TRM, Version 1.0
Bit 1
Bit 1
INTCAP[1:0]
MUX_CRx register on
AMUX_CFG register
Bit 0
Bit 0
Access
RW : 00
Access
RW : 00
RW : 00
RW : 00
RW : 00