CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 117

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

This chapter presents the Serial Peripheral Interconnect (SPI) and its associated registers. For a complete table of the SPI
registers, refer to the
isters in address order, refer to the
18.1
The Serial Peripheral Interconnect (SPI) block is a dedi-
cated master or slave SPI. The SPI slave function requires
three inputs: Clock, Data, and SS_ (unless the SS_ is forced
active with the SS_bit in the configuration register).
Figure 18-1. SPI Block Diagram
PSoC CY8C20x34 TRM, Version 1.0
18.
MOSI, MISO
SCLK
CONFIGURATION[7:0]
Architectural Description
SPI
TRANSMIT[7:0]
DATA_IN
CLK_IN
SYSCLK
SS_
“Summary Table of the System Resource Registers” on page
SPI Block
Registers
DATA_OUT
CLK_OUT
CONTROL[7:0]
RECEIVE[7:0]
Register Reference chapter on page
INT
MOSI, MISO
SCLK
18.1.1
The SPI is a Motorola™ specification for implementing full-
duplex synchronous serial communication between devices.
The 3-wire protocol uses both edges of the clock to enable
synchronous communication without the need for stringent
setup and hold requirements.
signals in a simple connection.
Figure 18-2. Basic SPI Configuration
A device can be a master or slave. A master outputs clock
and data to the slave device and inputs slave data. A slave
device inputs clock and data from the master device and
outputs data for input to the master. Together, the master
and slave are essentially a circular shift register, where the
Data is output by
both the Master
and Slave on
one edge of
the clock.
MISO
SPI Master
SCLK
MISO
MOSI
139.
SCLK
MOSI
SS_
SPI Protocol Function
90. For a quick reference of all PSoC reg-
Data is registered at
opposite edge of
the input of both
MOSI
SCLK
SS_
devices on the
SPI Slave
the clock.
Figure 18-2
MISO
shows the basic
117