CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 68

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

Band Gap
CLK32K
Sleep and Watchdog
9.4.3
During normal operation, the bandgap circuit provides a
voltage reference (VRef) to the system, for use in the analog
blocks, Flash, and low voltage detect (LVD) circuitry. Nor-
mally, the bandgap output is connected directly to the VRef
signal. However, during sleep, the bandgap reference gen-
erator block and LVD circuits are completely powered down.
The bandgap and LVD blocks are periodically re-enabled
during sleep in order to monitor for low voltage conditions.
This is accomplished by turning on the bandgap periodically,
allowing it time to start up for a full 32 kHz clock period, and
connecting it to VRef to refresh the reference voltage for the
following 32 kHz clock period as shown in
During the second 32 kHz clock period of the refresh cycle,
the LVD circuit is allowed to settle during the high time of
the 32 kHz clock. During the low period of the second 32
kHz clock, the LVD interrupt is allowed to occur.
Figure 9-3. Bandgap Refresh Operation
The rate at which the refresh occurs is related to the 32 kHz
clock and controlled by the Power System Sleep Duty Cycle
(PSSDC).
The default setting (256 sleep timer counts) is applicable for
many applications, giving a typical average device current
under 5 µA.
Table 9-1. Power System Sleep Duty Cycle Selections
68
VRef
Bandgap is turned on,
but not yet connected
leaking to ground.
00b (default)
VRef is slowly
PSSDC
01b
10b
11b
to VRef.
Table 9-1
Bandgap Refresh
enumerates the available selections.
Sleep Timer Counts
Voltage is refreshed.
connected to VRef.
Bandgap output is
active during CLK32K low.
Low voltage monitors are
1024
256
64
16
Figure
Bandgap is powered
Period (Nominal)
down until next
refresh cycle.
31.2 ms
500 µ s
8 ms
2 ms
9-3.
WD COUNT
WD RESET
SLEEP INT
9.4.4
On device boot up, the Watchdog Timer (WDT) is initially
disabled. The PORS bit in the system control register con-
trols the enabling of the WDT. On boot, the PORS bit is ini-
tially set to '1', indicating that either a POR or XRES event
has occurred. The WDT is enabled by clearing the PORS
bit. Once this bit is cleared and the watchdog timer is
enabled, it cannot be subsequently disabled. (The PORS bit
cannot be set to '1' in firmware; it can only be cleared.)
The only way to disable the Watchdog function, after it is
enabled, is through a subsequent POR or XRES. Although
the WDT is disabled during the first time through initializa-
tion code after a POR or XRES, all code should be written
as if it is enabled (that is, the WDT should be cleared period-
ically). This is because, in the initialization code after a WDR
event, the watchdog timer is enabled so all code must be
aware of this.
The watchdog timer is three counts of the sleep timer inter-
rupt output. The watchdog interval is three times the
selected sleep timer interval. The available selections for the
watchdog interval are shown in
timer interrupt is asserted, the watchdog timer increments.
When the counter reaches three, a terminal count is
asserted. This terminal count is registered by the 32 kHz
clock. Therefore, the WDR (Watchdog Reset) signal will go
high after the following edge of the 32 kHz clock and be held
asserted for one cycle (30 µs nominal). The flip-flop that
registers the WDT terminal count is not reset by the WDR
signal when it is asserted, but is reset by all other resets.
This timing is shown in
Figure 9-4. Watchdog Reset
Once enabled, the WDT must be periodically cleared in firm-
ware. This is accomplished with a write to the RES_WDT
register. This write is data independent, so any write will
clear the watchdog timer. (Note that a write of 38h will also
clear the sleep timer.) If for any reason the firmware fails to
clear the WDT within the selected interval, the circuit will
assert WDR to the device. WDR is equivalent in effect to
any other reset. All internal registers are set to their reset
state, see the table titled
Resets” on page
about WDT resets is that RAM initialization can be disabled
(IRAMDIS in the CPU_SCR1 register). In this case, the
SRAM contents are unaffected; so that when a WDR
occurs, program variables are persistent through this reset.
In practical application, it is important to know that the
watchdog timer interval can be anywhere between two and
CLK32K
(WDR)
Watchdog Timer
2
114. An important aspect to remember
PSoC CY8C20x34 TRM, Version 1.0
Figure
“Details of Functionality for Various
9-4.
3
Table
9-1. When the sleep
0