CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 111

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

16.3.2
The System Status and Control Register 0 (CPU_SCR0) is
used to convey the status and control of events for various
functions of a PSoC device.
Bit 7: GIES. Global Interrupt Enable Status. This bit is a
read only status bit and its use is discouraged. The GIES bit
is a legacy bit which was used to provide the ability to read
the GIE bit of the CPU_F register. However, the CPU_F reg-
ister is now readable. When this bit is set, it indicates that
the GIE bit in the CPU_F register is also set which, in turn,
indicates that the microprocessor will service interrupts.
Bit 5: WDRS. WatchDog Reset Status. This bit may not be
set. It is normally ‘0’ and automatically set whenever a
watchdog reset occurs. The bit is readable and clearable by
writing a zero to its bit position in the CPU_SCR0 register.
Bit 4: PORS. Power On Reset Status. This bit, which is the
watchdog enable bit, is set automatically by a POR or Exter-
nal Reset (XRES). If the bit is cleared by user code, the
watchdog timer is enabled. Once cleared, the only way to
reset the PORS bit is to go through a POR or XRES. Thus,
there is no way to disable the watchdog timer other than to
go through a POR or XRES.
PSoC CY8C20x34 TRM, Version 1.0
0,FFh
LEGEND
#
XX The reset value is 10h after POR/XRES and 20h after a watchdog reset.
Address
Access is bit specific. Refer to register detail for additional information.
CPU_SCR0
CPU_SCR0 Register
Name
GIES
Bit 7
Bit 6
WDRS
Bit 5
PORS
Bit 4
Bit 3: Sleep. This bit is used to enter Low Power Sleep
mode when set. To wake up the system, this register bit is
cleared asynchronously by any enabled interrupt. There are
two special features of this bit that ensures proper Sleep
operation. First, the write to set the register bit is blocked, if
an interrupt is about to be taken on that instruction boundary
(immediately after the write). Second, there is a hardware
interlock to ensure that, once set, the Sleep bit may not be
cleared by an incoming interrupt until the sleep circuit has
finished performing the sleep sequence and the system-
wide power down signal has been asserted. This prevents
the sleep circuit from being interrupted in the middle of the
process of system power down, possibly leaving the system
in an indeterminate state.
Bit 0: STOP. This bit is readable and writeable. When set,
the PSoC M8C will stop executing code until a reset event
occurs. This can be either a POR, WDR, or XRES. If an
application wants to stop code execution until a reset, the
preferred method would be to use the HALT instruction
rather than a register write to this bit.
For additional information, refer to the
on page
Sleep
Bit 3
182.
Bit 2
Bit 1
CPU_SCR0 register
STOP
Bit 0
System Resets
Access
# : XX
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