CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 99

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

14.2
14.2.1
When the IC slave operation is enabled, it is continually lis-
tening to or on the bus for a Start condition. When detected,
the transmitted Address/RW byte is received and read from
the I2C block by firmware. At the point where eight bits of
the address/RW byte have been received, a byte complete
interrupt is generated. On the following low of the clock, the
bus is stalled by holding the SCL line low, until the PSoC
device has had a chance to read the address byte and com-
pare it to its own address. It will issue an ACK or NACK
command based on that comparison.
PSoC CY8C20x34 TRM, Version 1.0
START
1
Application Overview
7-Bit Address
Slave Transmitter/Reciever
Slave Operation
7
generated. The SCL line
A byte interrupt is
is held low.
R/W
8
received byte from the
I2C_DR register and
Address” and R/W.
checks for “Own
M8C reads the
SHIFTER
byte to transmit
SHIFTER
M8C writes the
to the I2C_DR
register.
Figure 14-3. Slave Operation
M8C writes
(ACK | TRANSMIT) to
I2C_SCR
(ACK) to
register.
I2C_SCR register.
M8C writes
ACK
ACK
9
If there is an address match, the RW bit determines how the
PSoC device will sequence the data transfer in Slave mode,
as shown in the two branches of
ing methodology (slave holds the SCL line low to “stall” the
bus) will be used as necessary, to give the PSoC device
time to respond to the events and conditions on the bus.
Figure 14-3
transfer from the slave perspective.
1
1
8-Bit Data
8-Bit Data
An interrupt is generated
on byte complete. The
is a graphical representation of a typical data
SCL line is held low.
ACK/NACK. The SCL line
An interrupt is generated
7
7
on a complete byte +
is held low.
8
8
the I2C_DR register.
received byte from
M8C reads the
SHIFTER
NACK
ACK/
9
Figure
I2C_DR register and then writes
M8C writes a new byte to the
I2C_SCR to release the bus.
a TRANSMIT command to
I2C_SCR register.
M8C issues ACK/
with a write to the
NACK command
says end-of-data
NACK = Master
NACK
ACK/
ACK = Master
wants to read
another byte.
9
14-3. I2C handshak-
Slave says no
NACK =
another byte
STOP
Master may
more
I2C Slave
or STOP.
transmit
receive more
ACK = OK to
STOP
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