CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 55

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

6.1.5
Each GPIO pin can be individually configured for interrupt
capability. Pins are configured by pin interrupt enables and
also by a chip-wide selection for interrupt state with this glo-
bal selection. Pins can be set to interrupt when the pin is low
or when it changes from the last time it was read. The block
provides an open-drain interrupt output (INTO) that is con-
nected to other GPIO blocks in a wire-OR fashion.
All pin interrupts that are wire-OR’ed together are tied to the
same system GPIO interrupt. Therefore, if interrupts are
enabled on multiple pins, the user’s interrupt service routine
must provide a mechanism to determine which pin was the
source of the interrupt.
Using a GPIO interrupt requires the following steps:
1. Set the Interrupt mode (IOINT bit in the IO_CFG regis-
2. Enable the bit interrupt in the GPIO block.
3. Set the mask bit for the (global) GPIO interrupt.
4. Assert the overall Global Interrupt Enable.
The first step sets a common interrupt mode for all pins.
The second step, bit interrupt enable, is set at the GPIO pin
level (that is, at each port pin), by way of the PRTxIE regis-
ters.
The last two steps are common to all interrupts and are
described in the
At the GPIO block level, asserting the INTO line depends
only on the bit interrupt enable and the state of the pin rela-
tive to the chosen Interrupt mode. At the PSoC device level,
due to their wire-OR nature, the GPIO interrupts are neither
true edge-sensitive interrupts nor true level-sensitive inter-
PSoC CY8C20x34 TRM, Version 1.0
ter).
GPIO Block Interrupts
Interrupt Controller chapter on page
IE (PRTxIE.n)
INBUF (from GPIO Block Diagram)
Port Read
D
Q
Figure 6-2. GPIO Interrupt Logic Diagram
IOINT
47.
rupts. They are considered edge-sensitive for asserting, but
level-sensitive for release of the wire-OR interrupt line.
If no GPIO interrupts are asserting, a GPIO interrupt will
occur whenever a GPIO pin interrupt enable is set and the
GPIO pin transitions (if not already transitioned) appropri-
ately high or low to match the interrupt mode configuration.
Once this happens, the INTO line will pull low to assert the
GPIO interrupt. This assumes the other system-level
enables are on, such as setting the global GPIO interrupt
enable and the Global Interrupt Enable. Setting the pin inter-
rupt enable may immediately assert INTO, if the Interrupt
mode conditions are already being met at the pin.
Once INTO pulls low, it will continue to hold INTO low until
one of these conditions change: (a) the pin interrupt enable
is cleared; (b) the voltage at pin transitions to the opposite
state; (c) in interrupt-on-change mode, the GPIO data regis-
ter is read thus setting the local interrupt level to the oppo-
site state; or (d) the Interrupt mode is changed so that the
current pin state does not create an interrupt. Once one of
these conditions is met, the INTO releases. At this point,
another GPIO pin (or this pin again) could assert its INTO
pin, pulling the common line low to assert a new interrupt.
Note the following behavior from this level-release feature. If
one pin is asserting INTO and then a second pin asserts its
INTO, when the first pin releases its INTO, the second pin is
already driving INTO and thus no change is seen (that is, no
new interrupt would be asserted on the GPIO interrupt).
Care must be taken, using polling or the states of the GPIO
pin and Global Interrupt Enables, to catch all interrupts
among a set of wire-OR GPIO blocks.
Figure 6-2
Interrupt Mode
shows the interrupt logic portion of the block.
IE
0
0
1
1
IOINT
0
1
0
1
Interrupt
Disabled
Disabled
Low
Change from last read
General Purpose IO (GPIO)
INTO
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