CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 32

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

CPU Core (M8C)
2.6
The register shown here is associated with the CPU Core (M8C). The register description has an associated register table
showing the bit structure. The grayed out bits in the table are reserved bits and are not detailed in the register description that
follows. Always write reserved bits with a value of ‘0’.
2.6.1
The M8C Flag Register (CPU_F) provides read access to
the M8C flags.
Bits 7 and 6: PgMode[1:0]. PgMode determines how the
CUR_PP, STK_PP, and IDX_PP registers are used in form-
ing effective RAM addresses for Direct Address mode and
Indexed Address mode operands. PgMode also determines
whether the stack page is determined by the STK_PP or
IDX_PP register. (See the
in the RAM Paging chapter.)
Bit 4: XIO. The IO Bank Select bit, also known as the regis-
ter bank select bit, is used to select the register bank that is
active for a register read or write. This bit allows the PSoC
device to have 512 8-bit registers and can be thought of as
the ninth address bit for registers. The address space
accessed when the XIO bit is set to ‘0’ is called the user
space, while the address space accessed when the XIO bit
is set to ‘1’ is called the configuration space.
Bit 2: Carry. The Carry flag bit is set or cleared in response
to the actions of several instructions. It can also be manipu-
lated by the flag-logic opcodes (for example, OR F, 4). See
2.6.2
These registers are related to the M8C block:
32
x,F7h
LEGEND
L The AND F, expr; OR F, expr; and XOR F, expr flag instructions can be used to modify this register.
x An “x” before the comma in the address field indicates that this register can be read or written to no matter what bank is used.
Address
CPU_SCR1 register on page
CPU_SCR0 register on page
Register Definitions
CPU_F
CPU_F Register
Related Registers
Name
Bit 7
“Register Definitions” on page 36
PgMode[1:0]
181.
182.
Bit 6
Bit 5
Bit 4
XIO
the PSoC Designer Assembly Language User Guide for
more details.
Bit 1: Zero. The Zero flag bit is set or cleared in response
to the result of several instructions. It can also be manipu-
lated by the flag-logic opcodes (for example, OR F, 2). See
the PSoC Designer Assembly Language User Guide for
more details.
Bit 0: GIE. The state of the Global Interrupt Enable bit
determines whether interrupts (by way of the interrupt
request (IRQ)) will be recognized by the M8C. This bit is set
or cleared by the user using the flag-logic instructions (for
example, OR F, 1). GIE is also cleared automatically when
an interrupt is processed, after the flag byte has been stored
on the stack, preventing nested interrupts. If desired, the bit
can be set in an interrupt service routine (ISR).
For GIE=1, the M8C samples the IRQ input for each instruc-
tion. For GIE=0, the M8C ignores the IRQ.
For additional information, refer to the
page
179.
Bit 3
Carry
Bit 2
PSoC CY8C20x34 TRM, Version 1.0
Bit 1
Zero
CPU_F register on
Bit 0
GIE
Access
RL : 02