CY8C20X34 CYPRESS [Cypress Semiconductor], CY8C20X34 Datasheet - Page 183

• Manufacturer Part Number: CY8C20X34
• Description: Technical Reference Manual (TRM)
• Manufacturer: CYPRESS [Cypress Semiconductor]

20.4
The following registers are all in bank 1 and are listed in address order. Registers that are in both Bank 0 and Bank 1 are
listed in address order in the section titled
20.4.1
This register is one of two registers whose combined value determines the unique Drive mode of each bit in a GPIO port.
In register PRTxDM0 there are four possible drive modes for each port pin. Two mode bits are required to select one of these
modes, and these two bits are spread into two different registers (PRTxDM0 and
the effected port pin (for example, Pin[2] in Port 0) is the same as the bit position of each of the two Drive Mode register bits
that control the Drive mode for that pin (for example, bit[2] in PRT0DM0 and bit[2] in PRT0DM1). The two bits from the two
registers are treated as a group. These are referred to as DM1 and DM0, or together as DM[1:0].
All Drive mode bits are shown in the sub-table below ([10] refers to the combination (in order) of bits in a given bit position);
however, this register only controls the least significant bit (LSb) of the Drive mode.
The upper nibble of the PRT3DM0 register will return the last data bus value when read and should be masked off prior to
using this information.
For additional information, refer to the
Bit
7:0
PSoC CY8C20x34 TRM, Version 1.0
Individual Register Names and Addresses:
PRT0DM0 : 1,00h
Access : POR
Bit Name
Drive Mode 0[7:0]
Name
Bank 1 Registers
PRTxDM0
Port Drive Mode Bit Register 0
7
PRT1DM0 : 1,04h
6
Description
Bit 0 of the Drive mode, for each of 8-port pins, for a GPIO port.
[1 0 ]
0 0b
0 1 b
1 0 b
1 1 b
Note A bold digit, in the table above, signifies that the digit is used in this register.
Register Definitions on page 57
Bank 0 Registers on page
Pull up
Strong
ITIZ
Open Drain Low
5
PRT2DM0 : 1,08h
Pin Output High
Resistive
Strong
High-Z
High-Z
4
Drive Mode 0[7:0]
RW : 00
140.
in the GPIO chapter.
3
Pin Output Low Notes
Strong
Strong
High-Z
Strong
PRTxDM1 on page
PRT3DM0 : 1,0Ch
2
disabled for zero power.
Reset state. Digital input
(PRTxDR register) set high.
I2C compatible mode. For digital
inputs, use this mode with data
bit
1,00h
184). The bit position of
1
PRTxDM0
1,00h
0
183