ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 189

Manufacturer Part Number

KIT EVAL FOR AT91SAM3U CORTEX

Manufacturer

Processor To Be Evaluated

Data Bus Width

Interface Type

Operating Supply Voltage

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

Board CD Docs

Rohs Compliant

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Manufacturer

Part Number:

Manufacturer:

Send Event on Pending bit:

0 = only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded

1 = enabled events and all interrupts, including disabled interrupts, can wakeup the processor.

When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not

waiting for an event, the event is registered and affects the next WFE.

The processor also wakes up on execution of an

Controls whether the processor uses sleep or deep sleep as its low power mode:

1 = deep sleep.

• SLEEPONEXIT

Indicates sleep-on-exit when returning from Handler mode to Thread mode:

0 = do not sleep when returning to Thread mode.

1 = enter sleep, or deep sleep, on return from an ISR.

Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.

6430D–ATARM–25-Mar-11

System Control Register

The SCR controls features of entry to and exit from low power state. See the register summary

Table 13-30 on page 180

instruction or an external event.

for its attributes. The bit assignments are:

SAM3U Series