ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 867

Manufacturer Part Number

KIT EVAL FOR AT91SAM3U CORTEX

Manufacturer

Processor To Be Evaluated

Data Bus Width

Interface Type

Operating Supply Voltage

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

Board CD Docs

Rohs Compliant

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Manufacturer

Part Number:

Manufacturer:

6430D–ATARM–25-Mar-11

The PWM master clock (MCK) is divided in the clock generator module to provide different

clocks available for all channels. Each channel can independently select one of the divided

The clock generator is divided in three blocks:

Each linear divider can independently divide one of the clocks of the modulo n counter. The

selection of the clock to be divided is made according to the PREA (PREB) field of the PWM

Clock register (PWM_CLK). The resulting clock clkA (clkB) is the clock selected divided by DIVA

(DIVB) field value.

After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) are set to 0. This implies

that after reset clkA (clkB) are turned off.

At reset, all clocks provided by the modulo n counter are turned off except clock ”MCK”. This sit-

uation is also true when the PWM master clock is turned off through the Power Management

• Before using the PWM macrocell, the programmer must first enable the PWM clock in the

Power Management Controller (PMC).

– a modulo n counter which provides 11 clocks: F

– two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and

SAM3U Series