ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 691

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

35.7.1
35.7.1.1
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Baud Rate Generator
Baud Rate in Asynchronous Mode
The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the
receiver and the transmitter.
The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode
Register (US_MR) between:
The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field
of the Baud Rate Generator Register (US_BRGR). If CD is programmed to 0, the Baud Rate
Generator does not generate any clock. If CD is programmed to 1, the divider is bypassed and
becomes inactive.
If the external SCK clock is selected, the duration of the low and high levels of the signal pro-
vided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the
signal provided on SCK must be at least 3 times lower than MCK in USART mode, or 6 in SPI
mode.
Figure 35-3. Baud Rate Generator
If the USART is programmed to operate in asynchronous mode, the selected clock is first
divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR).
The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8,
depending on the programming of the OVER bit in US_MR.
If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is
cleared, the sampling is performed at 16 times the baud rate clock.
• the Master Clock MCK
• a division of the Master Clock, the divider being product dependent, but generally set to 8
• the external clock, available on the SCK pin
SCK
Reserved
MCK/DIV
MCK
USCLKS
0
1
2
3
16-bit Counter
CD
USCLKS = 3
0
SYNC
CD
>1
1
0
1
0
OVER
Sampling
Divider
SAM3U Series
SAM3U Series
FIDI
0
1
SYNC
SCK
Baud Rate
Sampling
Clock
Clock
691
691