ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 464

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

28.7
28.8
28.9
464
Free Running Processor Clock
Programmable Clock Output Controller
Fast Startup
SAM3U Series
The free running processor clock (FCLK) used for sampling interrupts and clocking debug blocks
ensures that interrupts can be sampled, and sleep events can be traced while the processor is
sleeping. It is connected to Master Clock (MCK).
The PMC controls 3 signals to be output on external pins, PCKx. Each signal can be indepen-
dently programmed via the PMC_PCKx registers.
PCKx can be independently selected between the Slow Clock (SLCK), the Main Clock
(MAINCK), the PLLA Clock (PLLACK), the UTMI PLL Clock (UPLLCK) and the Master Clock
(MCK) by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a
power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx.
Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of
PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks
are given in the PCKx bits of PMC_SCSR (System Clock Status Register).
Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actu-
ally what has been programmed in the Programmable Clock registers.
As the Programmable Clock Controller does not manage with glitch prevention when switching
clocks, it is strongly recommended to disable the Programmable Clock before any configuration
change and to re-enable it after the change is actually performed.
The SAM3UE device allows the processor to restart in less than six microseconds while the
device is in Wait mode. The system enters Wait mode either by writing the WAITMODE bit at 1
in the PMC Clock Generator Main Oscillator Register (CKGR_MOR), of by executing the Wait-
ForEvent (WFE) instruction of the processor while the LPM bit is at 1 in the PMC Fast Startup
Mode Register (PMC_FSMR).
Important: Prior to asserting any WFE instruction to the processor, the internal sources of
wakeup provided by RTT, RTC and USB must be cleared and verified too, that none of the
enabled external wakeup inputs (WKUP) hold an active polarity. (
A Fast Startup is enabled upon the detection of a programmed level on one of the 16 wake-up
inputs (WKUP) or upon an active alarm form the RTC, RTT and USB High Speed Device Con-
troller. The polarity of the 16 wake-up inputs is programmable by writing the PMC Fast Startup
Polarity Register (SUPC_FSPR).
The Fast Restart circuitry, as shown in
startup signal to the Power Management Controller. As soon as the fast startup signal is
asserted, this automatically restarts the embedded 4/8/12 MHz Fast RC oscillator.
Figure
28-3, is fully asynchronous and provides a fast
6430D–ATARM–25-Mar-11