ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 810
![KIT EVAL FOR AT91SAM3U CORTEX](/photos/9/20/92037/atsam3u-ek_sml.jpg)
ATSAM3U-EK
Manufacturer Part Number
ATSAM3U-EK
Description
KIT EVAL FOR AT91SAM3U CORTEX
Manufacturer
Atmel
Type
MCUr
Datasheets
1.ATSAM3U-EK.pdf
(2 pages)
2.ATSAM3U-EK.pdf
(61 pages)
3.ATSAM3U-EK.pdf
(1171 pages)
4.ATSAM3U-EK.pdf
(53 pages)
Specifications of ATSAM3U-EK
Contents
Board
Processor To Be Evaluated
SAM3U
Data Bus Width
32 bit
Interface Type
RS-232, USB
Operating Supply Voltage
3 V
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex - M3
Silicon Core Number
SAM3U4E
Silicon Family Name
SAM3U
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT91SAM3U
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3U-EK
Manufacturer:
Atmel
Quantity:
10
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37.7.2
37.7.3
810
SAM3U Series
Data Transfer Operation
Read Operation
The High Speed MultiMedia Card allows several read/write operations (single block, multiple
blocks, stream, etc.). These kinds of transfer can be selected setting the Transfer Type (TRTYP)
field in the HSMCI Command Register (HSMCI_CMDR).
These operations can be done using the features of the DMA Controller.
In all cases, the block length (BLKLEN field) must be defined either in the mode register
HSMCI_MR, or in the Block Register HSMCI_BLKR. This field determines the size of the data
block.
Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions
are defined (the host can use either one at any time):
The following flowchart
DMAC facilities. In this example, a polling method is used to wait for the end of read. Similarly,
the user can configure the interrupt enable register (HSMCI_IER) to trigger an interrupt at the
end of read.
• Open-ended/Infinite Multiple block read (or write):
• Multiple block read (or write) with pre-defined block count (since version 3.1 and higher):
The number of blocks for the read (or write) multiple block operation is not defined. The card
will continuously transfer (or program) data blocks until a stop transmission command is
received.
The card will transfer (or program) the requested number of data blocks and terminate the
transaction. The stop command is not required at the end of this type of multiple block read
(or write), unless terminated with an error. In order to start a multiple block read (or write)
with pre-defined block count, the host must correctly program the HSMCI Block Register
(HSMCI_BLKR). Otherwise the card will start an open-ended multiple block read. The BCNT
field of the Block Register defines the number of blocks to transfer (from 1 to 65535 blocks).
Programming the value 0 in the BCNT field corresponds to an infinite block transfer.
(Figure
37-8) shows how to read a single block with or without use of
6430D–ATARM–25-Mar-11
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