ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 432

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.18.20 SMC Timings Register
Name:
Address:
Access:
Reset:
• TCLR: CLE to REN Low Delay
Command Latch Enable falling edge to Read Enable falling edge timing.
Latch Enable Falling to Read Enable Falling = (TCLR[3] * 64) + TCLR[2:0] clock cycles.
• TADL: ALE to Data Start
Last address latch cycle to the first rising edge of WEN for data input.
Last address latch to first rising edge of WEN = (TADL[3] * 64) + TADL[2:0] clock cycles.
• TAR: ALE to REN Low Delay
Address Latch Enable falling edge to Read Enable falling edge timing.
Address Latch Enable to Read Enable = (TAR[3] * 64) + TAR[2:0] clock cycles.
• OCMS: Off Chip Memory Scrambling Enable
When set to one, the memory scrambling is activated.
• TRR: Ready to REN Low Delay
Ready/Busy signal to Read Enable falling edge timing.
Read to REN = (TRR[3] * 64) + TRR[2:0] clock cycles.
• TWB: WEN High to REN to Busy
Write Enable rising edge to Ready/Busy falling edge timing.
Write Enable to Read/Busy = (TWB[3] * 64) + TWB[2:0] clock cycles.
• RBNSEL: Ready/Busy Line Selection
This field indicates the selected Ready/Busy Line from the RBN bundle.
• NFSEL: NAND Flash Selection
If this bit is set to one, the chip select is assigned to NAND Flash write enable and read enable lines drive the Error Correct-
ing Code module.
432
432
NFSEL
31
23
15
–
–
7
SAM3U Series
SAM3U Series
0x400E007C [0], 0x400E0090 [1], 0x400E00A4 [2], 0x400E00B8 [3]
SMC_TIMINGSx [x=0..3]
Read-write
0x00000000
30
22
14
–
–
6
TADL
RBNSEL
29
21
13
–
–
5
OCMS
28
20
12
–
4
27
19
11
3
26
18
10
2
TCLR
TWB
TRR
TAR
25
17
9
1
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
24
16
8
0