ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 380

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KIT EVAL FOR AT91SAM3U CORTEX

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Figure 25-27. NWAIT Latency

intenally synchronized

NWAIT signal

SAM3U Series

NWAIT Latency and Read/Write Timings

There may be a latency between the assertion of the read/write controlling signal and the asser-

tion of the NWAIT signal by the device. The programmed pulse length of the read/write

controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1

cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT

signal assertion. This is true in frozen mode as well as in ready mode. This is illustrated on

When EXNW_MODE is enabled (ready or frozen), the user must program a pulse length of the

read and write controlling signal of at least:

minimal pulse length = NWAIT latency + 2 resynchronization cycles + 1 cycle

NWAIT latency

2 cycle resynchronization

minimal pulse length

EXNW_MODE = 10 or 11

READ_MODE = 1 (NRD_controlled)

NRD_PULSE = 5

6430D–ATARM–25-Mar-11