ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 86

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.5.7.6
13.6
86
Fault handling
SAM3U Series
Exception return
If no higher priority exception occurs during exception entry, the processor starts executing the
exception handler and automatically changes the status of the corresponding pending interrupt
to active.
If another higher priority exception occurs during exception entry, the processor starts executing
the exception handler for this exception and does not change the pending status of the earlier
exception. This is the late arrival case.
Exception return occurs when the processor is in Handler mode and executes one of the follow-
ing instructions to load the EXC_RETURN value into the PC:
EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism
relies on this value to detect when the processor has completed an exception handler. The low-
est four bits of this value provide information on the return stack and processor mode.
10
The processor sets EXC_RETURN bits[31:4] to
it indicates to the processor that the exception is complete, and the processor initiates the
exception return sequence.
Table 13-10. Exception return behavior
Faults are a subset of the exceptions, see
ate a fault:
EXC_RETURN[3:0]
bXXX0
b0001
b0011
b01X1
b1001
b1101
b1X11
• a
• a
• an
shows the EXC_RETURN[3:0] values with a description of the exception return behavior.
POP
BX
– a bus error on:
– an instruction fetch or vector table load
– a data access
LDR
instruction with any register.
instruction that includes the PC
or
LDM
instruction with the PC as the destination.
Description
Reserved.
Return to Handler mode.
Exception return gets state from MSP.
Execution uses MSP after return.
Reserved.
Reserved.
Return to Thread mode.
Exception return gets state from MSP.
Execution uses MSP after return.
Return to Thread mode.
Exception return gets state from PSP.
Execution uses PSP after return.
Reserved.
“Exception model” on page
0xFFFFFFF
. When this value is loaded into the PC
79. The following gener-
6430D–ATARM–25-Mar-11
Table 13-