ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 818

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

37.7.6.3
818
SAM3U Series
Block Length is Not Multiple of 4, with Padding Value (ROPT field in HSMCI_DMA register set to 1)
When the ROPT field is set to one, The DMA Controller performs only WORD access on the bus
to transfer a non-multiple of 4 block length. Unlike previous flow, in which the transfer size is
rounded to the nearest multiple of 4.
3. Wait for XFRDONE in HSMCI_SR register.
1. Program the HSMCI Interface, see previous flow.
2. Program the DMA Controller
j.
k. The LLI_B.DMAC_SADDRx field in memory must be set with the starting address
l.
m. Program LLI_B.DMAC_CTRLAx with the following field’s values:
n. Program LLI_B.DMAC_CTRLBx with the following field’s values:
o. Program LLI_B.DMAC_CFGx memory location for channel x with the following
– FIFOCFG defines the watermark of the DMA channel FIFO.
– SRC_H2SEL is set to true to enable hardware handshaking on the destination.
– SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI
p. Program LLI_B.DMAC_DSCR with 0.
q. Program DMAC_CTRLBx register for channel x with 0. its content is updated with
r.
s. Enable Channel x writing one to DMAC_CHER[x]. The DMAC is ready and waiting
– ROPT field is set to 1.
Host Controller.
descriptor on the second byte oriented descriptor. When block_length[1:0] is equal
to 0 (multiple of 4) LLI_W.DMAC_DSCRx points to 0, only LLI_W is relevant.
descriptor will be byte oriented. This descriptor is referred to as LLI_B, standing for
Program the channel registers in the Memory for the second descriptor. This
LLI Byte oriented.
of the HSMCI_FIFO address.
The LLI_B.DMAC_DADDRx is not relevant if previous word aligned descriptor was
enabled. If 1, 2 or 3 bytes are transferred that address is user defined and not word
aligned.
–DST_WIDTH is set to BYTE.
–SRC_WIDTH is set to BYTE.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length[1:0]. (last 1, 2, or 3 bytes of the buffer).
–DST_INCR is set to INCR
–SRC_INCR is set to INCR
–FC field is programmed with peripheral to memory flow control mode.
–Both SRC_DSCR and DST_DSCR are set to 1 (descriptor fetch is disabled) or
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, DMA
field’s values:
the LLI fetch operation.
Program DMAC_DSCRx with the address of LLI_W if block_length greater than 4
else with address of LLI_B.
for request.
Next descriptor location points to 0.
Controller is able to prefetch data and write HSMCI simultaneously.
6430D–ATARM–25-Mar-11