ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 85

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.5.7.3
13.5.7.4
13.5.7.5
6430D–ATARM–25-Mar-11
Tail-chaining
Late-arriving
Exception entry
This mechanism speeds up exception servicing. On completion of an exception handler, if there
is a pending exception that meets the requirements for exception entry, the stack pop is skipped
and control transfers to the new exception handler.
This mechanism speeds up preemption. If a higher priority exception occurs during state saving
for a previous exception, the processor switches to handle the higher priority exception and initi-
ates the vector fetch for that exception. State saving is not affected by late arrival because the
state saved is the same for both exceptions. Therefore the state saving continues uninterrupted.
The processor can accept a late arriving exception until the first instruction of the exception han-
dler of the original exception enters the execute stage of the processor. On return from the
exception handler of the late-arriving exception, the normal tail-chaining rules apply.
Exception entry occurs when there is a pending exception with sufficient priority and either:
When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask regis-
ters, see
pending but is not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-arriving
exception, the processor pushes information onto the current stack. This operation is referred as
stacking and the structure of eight data words is referred as stack frame. The stack frame con-
tains the following information:
Immediately after stacking, the stack pointer indicates the lowest address in the stack frame.
Unless stack alignment is disabled, the stack frame is aligned to a double-word address. If the
STKALIGN bit of the Configuration Control Register (CCR) is set to 1, stack align adjustment is
performed during stacking.
The stack frame includes the return address. This is the address of the next instruction in the
interrupted program. This value is restored to the PC at exception return so that the interrupted
program resumes.
In parallel to the stacking operation, the processor performs a vector fetch that reads the excep-
tion handler start address from the vector table. When stacking is complete, the processor starts
executing the exception handler. At the same time, the processor writes an EXC_RETURN
value to the LR. This indicates which stack pointer corresponds to the stack frame and what
operation mode the was processor was in before the entry occurred.
• the processor is in Thread mode
• the new exception is of higher priority than the exception being handled, in which case the
• R0-R3, R12
• Return address
• PSR
• LR.
new exception preempts the original exception.
“Exception mask registers” on page
64. An exception with less priority than this is
SAM3U Series
85