ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 706

• Manufacturer Part Number: ATSAM3U-EK
• Description: KIT EVAL FOR AT91SAM3U CORTEX
• Manufacturer: Atmel
• Type: MCUr

Specifications of ATSAM3U-EK

• Contents: Board
• Processor To Be Evaluated: SAM3U
• Data Bus Width: 32 bit
• Interface Type: RS-232, USB
• Operating Supply Voltage: 3 V
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Silicon Core Number: SAM3U4E
• Silicon Family Name: SAM3U
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT91SAM3U
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

35.7.3.8
706
706
SAM3U Series
SAM3U Series
Parity
The USART supports five parity modes selected by programming the PAR field in the Mode
Register (US_MR). The PAR field also enables the Multidrop mode, see
page
If even parity is selected, the parity generator of the transmitter drives the parity bit to 0 if a num-
ber of 1s in the character data bit is even, and to 1 if the number of 1s is odd. Accordingly, the
receiver parity checker counts the number of received 1s and reports a parity error if the sam-
pled parity bit does not correspond. If odd parity is selected, the parity generator of the
transmitter drives the parity bit to 1 if a number of 1s in the character data bit is even, and to 0 if
the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received
1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is
used, the parity generator of the transmitter drives the parity bit to 1 for all characters. The
receiver parity checker reports an error if the parity bit is sampled to 0. If the space parity is
used, the parity generator of the transmitter drives the parity bit to 0 for all characters. The
receiver parity checker reports an error if the parity bit is sampled to 1. If parity is disabled, the
transmitter does not generate any parity bit and the receiver does not report any parity error.
Table 35-9
depending on the configuration of the USART. Because there are two bits to 1, 1 bit is added
when a parity is odd, or 0 is added when a parity is even.
Table 35-9.
When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status
Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with
the RSTSTA bit to 1.
Character
707. Even and odd parity bit generation and error detection are supported.
A
A
A
A
A
shows an example of the parity bit for the character 0x41 (character ASCII “A”)
Parity Bit Examples
Figure 35-22
Hexa
0x41
0x41
0x41
0x41
0x41
illustrates the parity bit status setting and clearing.
0100 0001
0100 0001
0100 0001
0100 0001
0100 0001
Binary
Parity Bit
None
1
0
1
0
“Multidrop Mode” on
6430D–ATARM–25-Mar-11
6430D–ATARM–25-Mar-11
Parity Mode
Space
None
Even
Mark
Odd