ATSAM3U-EK Atmel, ATSAM3U-EK Datasheet - Page 562

Manufacturer Part Number

KIT EVAL FOR AT91SAM3U CORTEX

Manufacturer

Processor To Be Evaluated

Data Bus Width

Interface Type

Operating Supply Voltage

Silicon Manufacturer

Core Architecture

Core Sub-architecture

Silicon Core Number

Silicon Family Name

Kit Contents

Board CD Docs

Rohs Compliant

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Manufacturer

Part Number:

Manufacturer:

This register can only be written if the WPEN bit is cleared in

• CKS: Receive Clock Selection

• CKO: Receive Clock Output Mode Selection

• CKI: Receive Clock Inversion

0 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal

output is shifted out on Receive Clock rising edge.

1 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal out-

put is shifted out on Receive Clock falling edge.

CKI affects only the Receive Clock and not the output clock signal.

SAM3U Series

SSC Receive Clock Mode Register

Divided Clock

TK Clock signal

Continuous Receive Clock

Receive Clock only during data transfers

“SSC Write Protect Mode Register”

6430D–ATARM–25-Mar-11